A new low cost cascaded transformer multilevel inverter topology using minimum number of components with modified selective harmonic elimination modulation Academic research paper on "Electrical engineering, electronic engineering, information engineering"

Ain Shams Engineering Journal (2014) xxx, xxx-xxx

Ain Shams University Ain Shams Engineering Journal

www.elsevier.com/locate/asej www.sciencedirect.com

ELECTRICAL ENGINEERING

A new low cost cascaded transformer multilevel inverter topology using minimum number of components with modified selective harmonic elimination modulation

H. Khounjahan a, M.R. Banaei b'*, Amir Farakhor b

a Azarbayjan Regional Electric Company, Iran

b Electrical Engineering Department, Faculty of Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran Received 28 March 2014; revised 19 July 2014; accepted 17 August 2014

KEYWORDS

Cascaded transformers multilevel inverter; Reduced number of switching devices; Selective harmonic elimination

Abstract In this paper, a novel cascaded transformer multilevel inverter is proposed. The number of the switching devices is reduced in the proposed topology. This topology comprises of a DC source, several single phase low-frequency transformers, two main power switches and some bidirectional switching devices. In this topology, only one bidirectional switch is employed for each transformer. However, in conventional cascaded transformer multilevel inverter, four switching devices are required for each transformer. Therefore, more output voltage levels can be obtained using fewer switching components. Reduction in the number of switching devices which also means reduction in the number of gate drivers results in smaller size and low implementation cost. Switching power losses are also reduced in this topology. Selective harmonic elimination (SHE) technique is applied to the proposed inverter to obtain a high quality output voltage. Simulation and experimental results are also provided to verify the feasibility of the proposed converter.

© 2014 Production and hosting by Elsevier B.V. on behalf of Ain Shams University.

* Corresponding author.

E-mail addresses: Hosseinkhounjahan@yahoo.com (H. Khounjahan), M.banaei@azaruniv.edu (M.R. Banaei), Amir.farakhor.2013@ieee. org (A. Farakhor).

Peer review under responsibility of Ain Shams University

1. Introduction

During the past few years, multilevel inverters have played a major role in most systems such as large motor drives, flexible AC transmission systems, power quality improvement devices and renewable energy converters [1-3]. Therefore, multilevel inverters have attracted great attention of power electronic engineers. Multilevel inverters benefit from various advantages such as lower switching losses, stepwise output voltage, smaller common mode voltage and lower peak inverse voltage (PIV)

Production and hosting by Elsevier

http://dx.doi.org/10.1016/j.asej.2014.08.005

2090-4479 © 2014 Production and hosting by Elsevier B.V. on behalf of Ain Shams University.

on switches [4-6]. These advantages make multilevel inverters favorable for many industrial applications.

There are primarily three multilevel converter topologies so-called diode-clamped [7], flying capacitor [8] and cascaded H-bridge with separate DC sources [9]. They provide stepwise voltage with high quality. However, their main disadvantage, which is the excessive number of switching components, restrains their applications. In diode-clamped configuration, regulating the capacitors voltages makes the control scheme complicated. Also, abundant numbers of clamping diodes are required in this topology. Ladder structure of capacitors is used in flying capacitor multilevel inverters. Therefore the volume of the system is enlarged for the necessity of more capacitors. Cascaded H-bridge structure has the advantage of being modular which makes this structure easily expandable for higher number of output voltage levels. However, the need for separate DC voltage sources for each module and the number of switching components are the main disadvantages for this configuration. For overcoming these problems, novel topologies of multilevel inverters are presented in recent years. The cascaded transformer multilevel topology is proposed [10,11]. This topology employs one single DC voltage source and several isolated low-frequency transformers. However, number of switching components is still to be reduced. In [12,13], new topologies are proposed in order to reduce the number of switches. Therefore, the main disadvantage of cascaded transformer inverter is that this topology has many switching components.

Switching strategies of multilevel inverters are categorized into high switching frequency methods such as SPWM strategy [14] and low switching frequency techniques, often equal to fundamental switching frequency of the components, which create stepwise output voltage waveform [15]. Second category comprises of three major switching strategies so-called optimized harmonic stepped waveform [16], selective harmonic mitigation PWM [17], and optimal minimization of the THD [18]. Selective harmonic elimination is as effective method to mitigate the low-order harmonic components.

In this paper, a cascaded H-bridge reduced switch multilevel inverter is proposed which comprises of several low-frequency transformers. The number of switching components and gate drivers are minimized in this topology which reduced the size and the cost of realization. Selective harmonic elimination technique is employed to reach to a high quality output voltage. Simulation and experimental results indicate the ability of the proposed topology in voltage generating.

2. Cascaded transformer H-bridge multilevel inverter

In this section the traditional topology and two new topologies introduced for transformer based multilevel inverters are reviewed. Traditional cascaded H-bridge cells multilevel inverter needs several numbers of semiconductors and separated DC sources, these several numbers of isolated sources and components are difficult to be provided and controlled so this is a serious drawback for this topology. To eliminate need for several isolated DC sources the cascaded transformer H-bridge multilevel was introduced in which the transformers are used instead of DC sources. Attempting reach to a less component topology and obtain an optimized topology have led to appear some new topology which utilize fewer semiconductors and

Figure 1 (a) The traditional cascaded transformer multilevel inverter, (b) the CTITS topology.

DC sources. Cascaded transformer inverter with two DC sources (CTITS) is one of the newest less component topologies of transformer based multilevel inverter which have been introduced in [19]. Fig. 1a and b show traditional topology of cascaded transformer multilevel inverter and the CTITS respectively.

3. Proposed inverter structure

Fig. 2 shows the proposed cascaded multilevel inverter. This topology consists of a DC voltage source and several single phase transformers. As it is shown in Fig. 2, two main switching devices are used to change the polarity of the input voltage and for each transformer a bidirectional power switch is used.

Figure 2 Circuit diagram of the proposed multilevel inverter.

Table 1 Switching pattern for 9 level inverter.

Steps Switches position [1 = on & 0 = off] Vout

Main switches Common switches

Sa Sb Si S2 S3 S4

1 1 0 1 1 1 0 Vdc

2 1 0 1 1 0 1 2Vdc

3 1 0 1 0 1 1 3Vdc

4 1 0 0 1 1 1 4 Vdc

0 0 0 1 1 1 1 0

-1 0 1 1 1 1 0 -Vdc

-2 0 1 1 1 0 1 -2Vdc

-3 0 1 1 0 1 1 -3Vdc

-4 0 1 0 1 1 1 -4Vdc

Figure 3 Current flow path in the proposed inverter.

—^Cascaded H-bridge 96

-•-The proposed inverter

11 5 9

7 15 27 35 49

Output Voltage Levels

Figure 4 Number of power switches to realize m-level voltage.

In comparison with the conventional cascaded H-bridge multilevel inverter, numbers of switching devices are decreased. Respectively, the numbers of the gate drivers are reduced. Compare to the traditional transformer based multilevel inverters, using less switching devices as well as gate drivers in the proposed topology leads to cutting down in power losses, smaller size and low cost. In the proposed configura-

tion, the number of switches required to obtain an m-level output voltage can be given as follows:

SW = (m + 1)

(m + 3) 2

where SW, D and N are the number of the unidirectional switches, gate driver circuits and transformers respectively.

The secondary sides of the transformers are connected in series to synthesize the stepwise output voltage. The output phase voltage can be given by summing the output voltages of the transformers as below:

Von a Vdc 1 n

Vout = ^^m (1)

where Vn ,

a, Vout and n are the secondary voltage of each transformer, transformer ratio of transformers, output voltage of the inverter and number of cascaded transformers.

3.1. Operation of the proposed inverter

In the proposed inverter, each transformer can generate three voltage levels zero, + Vdc and — Vdc. The secondary sides of the transformers are series connected. Therefore, the maximum voltage can be generated from the configuration shown in Fig. 2 is +nVdc where n is the number of transformers. Different switching states and their corresponding output voltage for the proposed inverter are shown in Table 1. For symmetric operation of the inverter, turn ratios of the transformers are chosen to be the same. The current flow path of the proposed inverter is also shown in Fig. 3.

3.2. Voltage and current ratings of the switches

The most important criteria for selecting the proper power switches are peak inverse voltage (PIV) and current ratings of the switches. Assuming the input voltage as Vdc, in the proposed topology the maximum PIV of each bidirectional switches is Vdc/2, whereas each bidirectional switch is consists of two unidirectional switches it can be concluded that the maximum PIV of each switch is Vdc/4. However, the main switches have the maximum PIV of Vdc. Comparing the PIV of switches in the proposed topology to the traditional topology in which each switch is exposed to the maximum PIV of Vdc it is deducible that employing switches with a remarkable reduction on PIV is one of the most significant benefits of the proposed topology.

Table 2 Comparison study of mentioned topologies.

Inverter type The traditional topology The CTITS The proposed topology

Numbers of levels Transformers Unidirectional switches Gate driver circuits m (m - 1)/2 2 * (m - 1) 2 * (m - l) m (m - 1)/2 2 * (m - 1) 3/2 * (m - 1) m (m - 1)/2 (m + 1) (m + 3)/2

Vref ▲

4Vdc 3Vdc 2Vdc Vdc

ai a2 a3 a4 as as a? as a» aio aii ai2n/2

Figure 5 Half cycle phase voltage of a 9-level inverter.

Figure 6 Optimum switching angles versus modulation index.

The current ratings of the switching devices are different from each other in the proposed inverter. Considering the load current as 1 Pu, the current ratings of the main switches are 4 Pu in the inverter shown in Fig. 3. The current ratings of the transformer switches vary from 1 Pu to 4 Pu. Using switches with higher and various current rating is the main disadvantage of the proposed inverter.

3.3. Comparison study

This paper aims to reduce the number of components used in multilevel inverters. Among the conventional cascaded multilevel inverters, cascaded H-bridge requires a few numbers of

Discrete, Ts = 5e-005 s.

HHVf—L

powergui

fN fN TO -O

a -ICE

a -ICE

-»- a

a -»-

Figure 7 Simulation model of the proposed topology.

Table 3 Components specification of Simulation model.

Components Specification

Input .source

DC source (V) 10

Switches

Semiconductor IGBT/Diod

Internal resistance Ron (Ohms) 1e-3

Snubber resistance Rs (Ohms) 1e5

Transformers

Nominal power and frequency [500 60]

[Pn (VA) fn (Hz)]

Winding 1 parameters [12 0.072 9.1673e-004]

[V1 (Vrms) R1 (Pu) L1 (Pu)]

Winding 2 parameters [12 0.216 2.1e-6]

[V2 (Vrms) R2 (Pu) L2 (Pu)]

Magnetization resistance and [147.46 0.39114]

inductance [Rm (Pu) Lm (Pu)]

Load (series connected R-L)

Resistance (Ohms) 100

Inductance (H) 0.18

Reference waveform

Maximum magnitude (V) 40

Frequency (Hz) 60

shown in Fig. 5, the number of switching in each level is three. Fourier analysis of Fig. 5 is given as follows:

components. Number of switching components in conventional cascaded transformers inverter and the proposed inverter is compared in Fig. 4. As it can be seen in Fig. 4, the proposed topology requires fewer switching components for realizing m-level output voltage. For instance, seven-level output voltage is obtained using five switches in the proposed inverter. However, twelve switches are required for the same output voltage in cascaded transformers multilevel inverter. Additionally, there is a gate driver for each switch. As we reduce the number of switching components, the number of gate drivers is decreased too. Therefore, reduction of switches minimizes the cost and the size of the system. To provide more investigation the proposed topology is compared with two other topologies of cascaded transformer inverters that are introduced before. Table 2 exhibits the comparison of the proposed topology, the CTITS and the traditional cascaded transformer inverter.

4. Switching strategy

In multilevel inverters, modulation methods are necessary to obtain a high quality output voltage [20]. Many modulation techniques have developed recently such as pulse with modulation (PWM) and space vector modulation (SVM). Among these techniques, selective harmonic elimination (SHE) and THD minimization approaches are applied to multilevel inverters in order to eliminate harmonic components of the output voltage. SHE method aims to select the switching angles so that the low-order harmonics of the output voltage could be eliminated [21]. In this paper, SHE-PWM method is applied to a 9-level inverter. In this method, each level in switched several times in a period in order to increase the degrees of freedom (DOF) in our equations [22]. Fig. 5 illustrates the half-cycle output voltage of the inverter. As it is

_ 4 /np\

Va = _ Vdc sin ("H [cos (waO- cos(na2) -

+ cos(na4)- •

- cos ( na3 )

- cos (na12 )] sin (nxt)

The main purpose of SHE-PWM approach is to determine ai — ai2 such that the selected harmonic components are suppressed. In this paper, evolutionary algorithms are used to

determine the proper switching angles. A recently developed Imperialist Competitive Algorithm (ICA) is employed [23]. Using ICA algorithm, an objective function will be minimized and the optimum switching angles will be determined. The objective function is considered as follows:

Objective : 100

I V31 I

where M is the modulation index and n is the number of transformers. The corresponding optimum switching angles versus the modulation index is depicted in Fig. 6.

5. Simulation results

In order to demonstrate the operation of the proposed inverter, the configuration shown in Fig. 3 is simulated using MAT-LAB/Simulink software. Fig. 7 shows the simulation model of proposed topology. Specifications of the assumed structure for simulation acts are listed in Table 3 According to the optimum switching angles determined by ICA algorithm, the input voltages of the transformers are shown in Fig. 8a-d. As it is mentioned above to obtain a multilevel output voltage the secondary sides of the transformers are series connected. Therefore, the output voltage is the sum of the outputs of the transformers. The waveforms of the output voltage and load current are shown in Fig. 9. Because the magnitude of load current is much smaller than output voltage to make it explicit in the presence of output voltage its magnitude is multiplied to 50; the harmonic spectrum of the output voltage and current is depicted in Fig. 10a and b respectively. According to these figures the THD of output voltage is 11.52% however the simulated output voltage contain third harmonic and its submultiples which can be eliminated in three phase application this amount of THD is acceptable. Since the inductive feature of the load makes the waveform of the load current more sinusoidal the load current has lower THD.

6. Experimental results

The circuit configuration, shown in Fig. 2, is used to verify the operation of the proposed inverter. A hardware prototype 9-level inverter is implemented as shown in Fig. 11. This inverter consists of four transformers, two main switches and four bidi-

0.19 0.195 0.2 0.205 0.21 0.215 0.22 0.225 0.23 Time (sec)

Figure 9 Waveforms of (a) output voltage, (b) output current.

if 100 c

E 80 ro ■a § 60 LI'S 40 g.

§ 60 u_

Fundamental (50Hz) = 41.53 , THD= 11.52%

2 1 l 1 i 1 i

0 _j J l

Harmonic order

Fundamental (50Hz) = 0.2522 , THD= 2.35%

0 0

0 5 10 15 2

Harmonic order

Figure 10 Harmonic spectrum of (a) output current, (b) output voltage.

Figure 11 Picture of the hardware implementation.

Table 4 Prototype components specification.

Components Specification

Switches Gate insulator Buffer Snubber Processor IRFP250 TLP250 HC573 10 O + 20 iF DSP TMS320F28335

rectional transformer switches. Prototype components specifications are summarized in Table 4. The input DC voltage is 20 V. Whereas the performances of an inverter are appraised in the presence of a load with inductive load a series connected RL load is considered in the simulation and experimental acts. The feature of employed RL load at the output stage of the inverter is R = 140 X and L = 260 mH. In order to measure the load current voltage of a series resistance with R = 75 X is shown. Fig. 12 shows the output voltage and output current

Gïi inSTEK 0.000S _f*"~L

DO 3.3ms • EDGE

Figure 12 Measured (a) output voltage, (b) output current.

of the proposed inverter. As it is shown in Fig. 12, the output voltage is a stepwise symmetric waveform. The proposed inverter can efficiently minimize the number of components used in multilevel inverters. Also, results prove the ability of the proposed inverter in generating the desired output voltage. Furthermore according to Fig. 12 there appear some ramps on the steps of the output voltage these ramps are resulted from the dropped voltages over the leakage impedances of the transformers so they can be eliminated by using some optimized transformers that leads to obtain more high quality output voltage.

7. Conclusions

In this paper, a cascaded transformer multilevel inverter with reduced number of switching components is presented. The proposed topology utilizes low-frequency single-phase transformers and a DC voltage source. This configuration can reduce the number of switches in comparison with conventional cascaded transformer multilevel inverters. Selective harmonic elimination technique is applied to mitigate the low-order harmonic components. In order to verify the operation and performance of the proposed inverter, simulation and experimental results using a single-phase 9-level multilevel inverter prototype are provided.

References

[1] Lai JS, Peng FZ. Multilevel converters - a new breed of power converters. IEEE Trans Ind Appl 1996;32(3):509-17.

[2] Lezana P, Rodriguez J, Oyarzun DA. Cascaded multilevel inverter with regeneration capability and reduced number of switches. IEEE Trans Ind Electron 2008;55(3):1059-66.

[3] Panagis P, Stergiopolos F, Marabeas P, Manios S. Comparison of state of the art multilevel inverters. In: Proc power electronics specialists conf PESC 2008, IEEE; 2008. p. 4296-301.

[4] Meynard TA, Foch H, Forest F, et al. Multicell converters: derived topologies. IEEE Trans Ind Electron 2002;49(5):978-87.

[5] Du Z, Tolbert LM, Ozpineci B, Chiasson JN. Fundamental frequency switching strategies of a seven-level hybrid cascaded H-bridge multilevel inverter. IEEE Trans Power Electron 2009;24(1):25-33.

[6] Corzine KA, Familiant YL. A new cascaded multilevel H-bridge drive. IEEE Trans Power Electron 2002;17:125-31.

[7] Nabae A, Takahashi I, Akagi H. A new neutral-point clamped PWM inverter. IEEE Trans Ind Appl 1981;IA-17:518-23.

[8] Rodriguez J, Lai JS, Peng FZ. Multilevel inverter: a survey of topologies, controls, and applications. IEEE Trans Ind Electron 2002;49(4) :724-38.

[9] Cengelci E, Sulistijo SU, Woom BO, Enjeti P, Teodorescu R, Blaabjerge F. A new medium voltage PWM inverter topology for adjustable speed drives. In: Proc conf rec IEEE-IAS annual meeting, St. Louis, MO; October 1998. p. 1416-23.

[10] Barcenas E, Ramirez S, Cardenas V, Echavarria R. Cascaded multilevel inverter with only one dc source. In: Proc VIII IEEE int tech proc CIEP; 2002. p. 171-6.

[11] Park SJ, Kang FS, Cho SE, Moon CJ, Nam HK. A novel switching strategy for improving modularity and manufacturabil-ity of cascaded transformer based multilevel inverters. Electr Power Syst Res 2005;74(3):409-16.

[12] Banaei MR, Salary E. New multilevel inverter with reduction of switches and gate driver. Energy Convers Manage 2011;52:1129-36.

[13] Babaei E, Hosseini SH. New cascaded multilevel inverter topology with minimum number of switches. Energy Convers Manage 2009;50:2761-7.

[14] Saeedifard M, Iravani R, Pou J. Analysis and control of DC-capacitor-voltage-drift phenomenon of a passive front-end five-level converter. IEEE Trans Ind Electron 2007;54(6):3255-66.

[15] El-Naggar K, Abdelhamid TH. Selective harmonic elimination of new family of multilevel inverters using genetic algorithms. Energy Convers Manage 2008;49(1):89-95.

[16] Kaviani AK, Fathi SH, Farokhnia N, Ardakani AJ. PSO, an effective tool for harmonics elimination and optimization in multilevel inverters. In: Proc 4th IEEE ICIEA; May 25-27, 2009. p. 2902-7.

[17] Franquelo LG, Napoles J, Guisado RCP, Leon JI, Aguirre MA. A flexible selective harmonic mitigation technique to meet grid codes in three-level PWM converters. IEEE Trans Ind Electron 2007;54(6):3022-9.

[18] Sahali Y, Fellah MK. New approach for the symmetrical multilevel inverters control optimal minimization of the total harmonic distortion (OMTHD technique). In: Proc IEEE ISIE, Ajaccio, France, May 4-7, 2004.

[19] Banaei MR, Salary E, Alizadeh R, khounjahan H. Reduction of components in cascaded transformer multilevel inverter using two DC sources. J Electr Eng Technol 2012;7(4):538-45.

[20] Franquelo LG, Rodriguez J, Leon JI, Kouro S, Portillo R, Prats MM. The age of multilevel converters arrives. IEEE Ind Electron Mag 2008;2(2):28-39.

[21] Fei W, Du X, Wu B. A generalized half-wave symmetry SHE-PWM formulation for multilevel voltage inverters. IEEE Trans Industr Electron 2010;57(9):3030-8.

[22] Li L, Czarkowski D, Liu Y, Pillay P. Multilevel selective harmonic elimination PWM technique in series-connected voltage converters. IEEE Trans Ind Appl 2000;36(1):160-70.

[23] Khorani V, Razavi F, Disfani VR. A mathematical model for urban traffic and traffic optimization using a developed ICA technique. IEEE Trans Intell Transp Syst 2011;12(4).

Mohamad Reza Banaei was born in Tabriz, Iran. He received his M.Sc. degree from the Poly Technique University of Tehran, Iran, in control engineering in 1999 and his Ph.D. degree from the electrical engineering faculty of Tabriz University in power engineering in 2005. He is an Associate Professor in the Electrical Engineering Department of Azar-baijan Shahid Madani University, Iran, which he joined in 2005. His main research interests

include the modeling and controlling of power electronic converters,

renewable energy, modeling and controlling of FACTS and Custom

Power devices and power systems dynamics.