Scholarly article on topic 'SiGe HMODFET “KAIST” Micropower Model and Amplifier Realization'

SiGe HMODFET “KAIST” Micropower Model and Amplifier Realization Academic research paper on "Nano-technology"

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Academic research paper on topic "SiGe HMODFET “KAIST” Micropower Model and Amplifier Realization"

SiGe HMODFET "KAIST" Micropower Model and

Amplifier Realization

Antonio Vilches, Kristel Fobelets, Kostis Michelakis, Solon Despotopoulos, Christos Papavassiliou,

Thomas Hackbarth, and Ulf König

Abstract—The recently published small-signal KAIST model is used successfully to fit the measured RF characteristics of a novel SiGe n-HMODFET device operating at micropower levels and extracted small-signal model parameters for this device under micropower operation are presented here for the first time. This model is then used to predict the performance of a simple micropower amplifier (sub 300-^liW total power consumption), realized in SiGe technology, and a comparison of modeled versus measured data is included.

Index Terms—Micropower, modeling, MODFET, SiGe.

I. Introduction

WORK on buried channel SiGe/Si hetero-junction FET devices began in the early 1980s with a view to exploiting the higher mobilities offered by the strained channel in order to improve the speed of pMOS devices [1]. The work was then expanded to n-type HMODFET devices by fabricating the active n-type layers on relaxed p-type SiGe buffer layers, originally in [2] and [3], and more recently in [4]-[6]. It was soon realized that the increased mobility in buried channel devices, due to a lower subthreshold slope at low to high Vt, offered the prospect of reducing power supply levels for RF operation to what are here broadly termed micropower levels (sub 1-mW total power consumption) [7]. Such low-power, RF capable devices would clearly improve battery life and reduce overall heat dissipation in sensitive, long-term portable RF and biomedical applications.

Although a range of device fabrication techniques are under exploration including the use of a grown or sputtered gate oxide to reduce gate currents [8], [9] and fabrication on insulating substrates to reduce parasitic effects and so improve RF performance [10], [11], SiGe HMODFET device modeling for RF micropower applications is still at a very early stage and there is currently no published small-signal modeling data for SiGe virtual substrate (VS) n-HMODFET devices operating with a total power consumption of sub 300 fiW. In this paper, we report on the first-time use of the recently published KAIST small-signal model and simple, linear regression based parameter extrac-

Manuscript received June 16, 2003; revised November 18, 2003. This work was supported by the EPSRC under Award N. GR/N65844/01. This paper was recommended by Associate Editor H. Graeb.

A. Vilches and K. Fobelets are with Optical and Semiconductor Devices, Department of Electrical and Electronic Engineering, Imperial College London, London SW7 2BT, U.K. (e-mail: a.vilches@imperial.ac.uk).

K. Michelakis, S. Despotopoulos, and C. Papavassiliou are with Analogue Electronics, Department of Electrical and Electronic Engineering, Imperial College London, London SW7 2BT, U.K.

T. Hackbarth and U. König are with the DaimlerChrysler Research Center, D-89081 Ulm, Germany.

Digital Object Identifier 10.1109/TCSI.2004.829242

PadCC/2 PadCC/2

Fig. 1. A n-HMODFET device physical structure and equivalent circuit diagram.

5 nm n+-SiGe^40% : Sb supply

5 nm n-SiGe 40%^ supply

Silicon substrate: p- > 1000 Qcm Fig. 2. Device stack layer details.

tion process [12] for micropower small-signal RF modeling of n-HMODFET devices, which we find to be more suitable than the related approaches previously discussed in [14]-[20].

The device structure and fabrication is outlined in Section II-A, the extraction method used is briefly discussed in Section II-B, extracted small-signal parameters and modeled versus measured device comparison are presented in Section III-A, simulated versus realized micropower amplifier characteristics are given in Section III-B, and we conclude in Section IV.

II. Method A. Device Structure and Fabrication

A diagram of the device's physical layer structure overlaid with equivalent circuit small-signal circuit parameters is shown in Fig. 1; the stack layer details are given in Fig. 2, and Fig. 3 is an actual photomicrograph of the RF device under test (DUT). The transistors are "T" types, so called because they possess a single gate-pad driving a metal gate-finger split symmetrically between source and drain, as shown in Fig. 3. Devices of 0.1-^m gate length and 100-^m width were used for this investigation.

1057-7122/04$20.00 © 2004 IEEE

Fig. 4. Simplified diagram of the "open" structure. Source and drain metal contacts, denoted by letters "S" and "D," are separate.

Fig. 3. Photomicrograph of "T" type HMODFET device with gate, drain, and source contacts labeled.

The n-MODFET structure was grown by molecular beam epitaxy (MBE) on a 40% (Ge) graded VS, which was prepared by low-energy plasma enhanced chemical vapor deposition (LEP-ECVD). Free electrons are supplied into the 9-nm strained Si channel by two Sb-doped layers, which are situated on either side of the quantum well. These layers are separated from the channel through the use of undoped SiGe spacer layers to reduce scattering and further enhance the channel mobility. The structure is capped with a 6-nm SiGe layer and a thinner Si layer on top to ensure the highest possible quality for the metal Schottky gate.

A standard fabrication technique for n-type SiGe MODFETs was applied, which included dry MESA etching for electrical isolation of the epitaxial active areas and deposited field oxide for electrical isolation of the implanted areas. The ohmic contacts were implanted with P and were subsequently activated by rapid thermal annealing (RTA). The ohmic metal consisted of Ti/Pt/Au and was implemented by optical lithography, e-beam evaporation, and lift-off and is also used for circuit interconnections. The Pt/Au Schottky gates were defined by e-beam lithography plus lift-off. The minimum gate length available on-wafer is 0.1 /im. A number of test devices and structures were also included for characterization, among which were Hall patterns which were characterized at 300° CK. The measured sheet resistivity of the structure was 811 £}/□, the sheet electron density was 4.5 x 1012 cm-2, and the corresponding mobility was 1700 cm2/Vs (300°CK). Measured mean access resistance values of 3 f2-mm for drain and source resistances (RS and RD) were provided by the DaimlerChrysler foundry. The unusually high mean value of these access resistances is expected to dramatically reduce as the technology used matures and processing technique is improved.

B. Simulation, Modeling and Parameter Extraction

A HP5783D Network Analyzer was used to probe, bias and measure the fabricated devices and the recorded two-port s-parameters were converted into Y parameter sets, using MWOFFICE CAD software [21], for use in direct extraction and modeling.

Fig. 5. Simplified diagram of the "short"' structure. Source and drain metal contacts, denoted by letters "S" and "D," are shorted together.

Fig. 6. KAIST small-signal equivalent circuit model of the intrinsic device.

The device was biased in the subthreshold region: Vqs = — 0.8 V as this is close to its threshold voltage of — 0.88 V. A Vqs supply of 400 mV was used and the supply current for this setup was measured at 734 ¡¿A, giving a total supply power of 294 /iW.

The intrinsic device was de-embedded using the lumped-element de-embedding technique reported in [13] with the aid of further data sets measured from "open" and "short" devices located on-wafer close to the DUT, simplified diagrams of which are shown in Figs. 4 and 5. It was not considered necessary to model inductive parasitics as an s-parameter extracted track inductance value of 714 nH/m indicates that the effect of these at the frequencies dealt with would be negligible. The extraction process for the intrinsic device parameters (dm ? 9ds ? Rg, Cgd, Cgs, and Cdg) given by Kwon et al in [12] was then rigorously followed in order to obtain their values for the KAIST model shown in Fig. 6. The current sources I\ and

computed during simulation as given in (1) and (2) from [12] are

(1) (2)

r _ 1*^211 (j ^Max — "T7J-1 ( & '

|5n|2-|522|2 + A2

A — 5ii^22 — ^12^21

\Sl2\'

Confusion arose during the extraction of the substrate parameters when it was realized that the equation given for YSub> [12, eq. (15)] is a function of source-drain capacitance Csd. This parameter, it was claimed, is to be obtained from (18) in [12] after Ysub has been evaluated, as Csd is a function of both Rsubd and Cjd, which are both, in turn, functions of YSub- Private communication with the author on this issue confirmed that the inclusion of the term —jwCsa in equation for Ysub was a typographical error and that this term could be safely omitted from the calculation. It is to be noted also that the extracted value for Csd reported in [12] is small and negative (—3.1 fF) as it is in our own extraction and this casts doubt on the validity of the use of this parameter in the model as it is suspected that Csd and Cjd combine to give an accurate value for Cjd- The remaining substrate parameters (Rsubd5 Cjd and Csd) were then extracted as explained in [12] only with the —jwCsd term omitted from the equation and the small-signal KAIST model together with a comparison of the modeled versus measured intrinsic device admittance versus frequency is given in the results section.

The extracted model is then used to simulate a simple Class-A micropower amplifier in MWOFFICE, with an input power level of — 25 dBm and a total power supply to the FET device of just 294 /iW. The FET is worked into a resistive 120-0 load, and no impedance matching is used as the circuit's bandwidth was expected to be low at the targeted micropower operation level; the circuit's input and output are terminated with standard 50-Q ports. Plots of power gain Cm ax (3) and maximum stable gain [MSG—(6)] are used in Section III-B to illustrate and compare the gain and bandwidth of both the simulated and measured amplifier response

Fig. 7. Extrinsic bonding-pad capacitance extraction versus frequency.

Fig. 8. Gate resistance extraction versus frequency. A mean extracted value of 141 is shown.

III. Results A. Device Model and Parameters

A plot of the de-embedded bonding-pad capacitances as a function of measurement frequency is shown in Fig. 7. A mean extracted value of 115 fF is shown for the drain and gate capacitances CpadD and CpadG, respectively, and a mean value of 4.8 fF is shown for the parasitic coupling capacitance between gate and drain, PadCC. The deviation from the expected mean values at low frequencies is due to a combination of current leakage in the pads and the inherent low frequency roll-off of the network analyzer's port couplers.

2001 4001

Frequency (MHz)

Fig. 9. Intrinsic capacitance extraction versus frequency.

Fig. 8 illustrates the extraction of the extrinsic resistance, Rg( 141 ii), and the extraction of the intrinsic capacitances is shown in Fig. 9. These charts are included here as the relative constancy of the values extracted attests to the adequacy of the de-embedment and modeling procedure followed, as does the —20 dB/Dec plot of intrinsic |H21|2 versus log(/) shown in Fig. 10. The plot of |

, computed from mod-eledintrinsic Y-parameter sets |i^2i|2 = (Y21ix/Yllix),also gives a clear —20 dB/Dec slope and this further attests to the quality of the modeling process. The bias scheme was chosen to ensure a useable micropower bandwidth where gm > and

versus

Fig. 10. Current gain |ii21|2 versus log(/). Embedded, extracted intrinsic and computed intrinsic (H21ix) plots are included.

Fig. 13. Intrinsic device Y12 measured (Y12i) versus modeled (Y12ix).

Fig. 11. Intrinsic voltage gain versus log(/). A unity-gain bandwidth of almost 3.5 GHz is notable.

Frequency (MHz

Fig. 14. Intrinsic device Y21 measured (Y21i) versus modeled (Y21ix).

2001 3001

Frequency (MHz)

Fig. 12. Intrinsic device Yll measured (Ylli) versus modeled (Yllix).

1 e-005

1 e-006

= V Re(Eqn) * Q im(Eqn) * -^g- Re(Eqn) * O Im(Eqn) * = Y22i Y22i Y22ix Y22ix -

|glP——

Frequency (MHz)

Fig. 15. Intrinsic device Y22 measured (Y22i) versus modeled (Y22ix).

the plot of intrinsic voltage gain Ay = (Y21i/Y22i), given in Fig. 11, shows a unity-gain bandwidth of ~3.5 GHz. It is worth noting that the access resistances contribute roughly 9% of the total channel resistance (ras = (l/#ds) = 667 RD + RS « 60 Q) and that as these are not part of the KAIST model, they can be expected to cause a small degree of error, but this error is expected to decrease as the technology improves and access resistance mean values are reduced.

Figs. 12-15 are the measured versus modeled intrinsic Y parameters, and a good similarity is evident in most, the greatest

error resulting in the real part of Y21 above 3.5 GHz, where 9m < #ds, and in the imaginary part of Y22 at low frequencies, due to a combination of current leakage and the fact that Y22 will be affected most by the effects of the total access resistance as both RS and RD form part of Y22-1. There is, in general, a good match at all frequencies below 3.5 GHz and as the bandwidth of any circuit employing these devices under micropower bias is unlikely to exceed this frequency, the model is acceptable for micropower RF design. A summary of all the extracted parameters is presented in Table I.

TABLE I

Exracted Model Parameters

Parameter Value

CpadG 115 fF

CpadD 115 fF

PadCC 4.8 fF

Qs 32 fF

Qd 17 fF

Cdg 2 fF

Csd - 1.3 fF

C\ d 9 fF

£ds 1.5 mS

gm 1.77 mS

^subd 70 Q

1.E+08 1.E+09

Frequency(Hz)

Fig. 16. MSG measured versus modeled.

Fig. 17. Gmax measured versus modeled.

B. Micropower Amplifier

The simulations in Figs. 16, and 17, show that a maximum power gain of 30 dB for Gmax and 32 dB for MSG, together with a nonimpedance matched bandwidth of around 100 MHz, is achievable at the chosen micropower bias levels and the amplifier measured response reflects the simulated trends closely.

IV. Conclusion

The RF characteristics of a novel SiGe n-HMODFET operated at micropower levels with total power = 294 ¡iW have been successfully fit to the KAIST small-signal model, and all related extracted model parameters have been presented here for the first time. The model has then been used to simulate the performance of a realized SiGe micropower amplifier using a similar

device and the measured versus simulated power gain and bandwidth comparison presented prove that this model is suitable for use in small-signal RF micropower simulations of HMODFET devices.

Acknowledgment

The authors wish to acknowledge the following: D. Chrastina and H. von Känel (Dipartimento di Fisica del Politecnico di Milano, INFM, Como, Italy) for device LEPECVD buffer growth; M. Zeuner, and J. Müller (DaimlerChrysler AG, Research Center Ulm, Ulm, Germany) for processes engineering.

References

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Antonio Vilches was born in London, U.K., in 1969. He received the graduate degree in electronic engineering from Salford University, Manchester, U.K., and the Ph.D. degree from Imperial College London, London, U.K., in 1996 and 2004, respectively.

Between 1996 and 2001, he worked for IBM, London, U.K., He is now a Research Assistant in the Circuits and Systems Research Group in the Electrical and Electronic Engineering Department, Imperial College London. His interests include microwave/photonic device modeling and circuit design for RF and micropower applications. He has coauthored more than ten publications in related fields.

Kristel Fobelets received the M.Sc. degree in the electrical engineering from the Free University, Brussels, Belgium, and the Ph.D. degree from IMEC, Brussels, Belgium, in 1989 and 1994, respectively.

She is currently a Senior Lecturer in the Electrical Engineering Department, Imperial College London, London, U.K. Her interests lie in the physics and applications of semiconductor devices based on new material systems or quantum mechanical effects in Si:SiGe and III-V materials, with the purpose of optimizing existing device/circuit applications in speed and functionality. Her current research concerns low-power analog strained-Si devices/circuits, low temperature strained-Si electronics and the development of alternative material analysis techniques. She is author and coauthor of more than 60 papers in technical journals and conference proceedings.

Dr. Fobelets is a member of the Center for Electronic Materials and Devices (CEMD), Imperial College London, U.K.

Solon Despotopoulos was born in Athens, Greece in 1971. He received the B.Sc.degree in physics and M.Sc. degree in electronics from the University of Patras, Patras, Greece, and the Ph.D. degree from Imperial College London, London, U.K., in 1993, 1997, and 2004, respectively. His Ph.D. dissertation focuses on characterizing SiGe MOSFETs and MODFETs and how to use them in order to build analog integrated circuits.

For the past year, he is developing a measuring instrument that collects data from various sensors within the fuel tank of an aircraft. His interests include FET device characterization and analog and digital circuit design used in sensor and actuator applications.

Christos Papavassiliou was born in Athens, Greece, in 1960. He received the B.S. degree in physics from Massachusetts Institute of Technology, Cambridge, and the Ph.D. degree in applied physics from Yale University, New Haven, CT.

He has worked on monolithic microwave integrated circuit (MMIC) design and measurements at FORTH, Crete, Greece and has been involved in several European and regional projects on GaAs MMIC technology. In 1996, he joined Imperial College London, London, U.K., where he is a Senior Lecturer. He currently works on SiGe technology development as well as instrumentation and substrate noise coupling in mixed mode integrated circuit

design. He has contributed to 30 publications.

Thomas Hackbarth was born on August 28, 1958 in Stade, Germany. He received the Ph.D. degree in electrical engineering from Technical University of Braunschweig, Braunschweig, Germany, in 1991.

He is with the Research Center of DaimlerChrysler, Ulm, Germany. His current interest is layer growth and device processing of SiGe field effect transistors and integrated circuits.

Kostis Michelakis was born in Chania, Greece, in 1963. He received the graduate degree in physics and the Master's degree in applied physics, from the University of Crete, Crete, Greece, and the Ph.D. degree from the University of Athens, Athens, Greece, in 1985, 1990, and 1994, respectively.

From 1994 to 1999, he was a Research Scientist and Clean Room Processing Engineer at the Microelectronics Research Group, FORTH, Crete, Greece. He spent one year at the CCLRC Daresbury Laboratory, Daresbury, U.K. He is currently a Research Fellow in the Department of Electrical and Electronic Engineering, Imperial College London, London, U.K. His fields of interest are in physics, technology and applications of III-V and Si-based heterojunction devices. He has authored and coauthored more than 25 papers in international refereed journals and he has been appointed a reviewer for Electronics Letters and for ISCAS 2003.

Ulf König received the Diploma in physics and the Ph.D. degree in electrical engineering from Rheinisch-Westfalische Technische Hochschule (RWTH), Aachen, Germany, in 1970 and 1973, respectively.

In 1975, he joined AEG Ulm, Ulm, Germany, which was later on taken over by DaimlerChrysler, and where, since 1992, he has been Headi of Department, working on SiGe growth, processes, devices, and circuits. He was responsible for the early transfer of the SiGe Hetero Bipolar Transistor technology into production and is presently promoting the introduction of the strained-silicon Hetero Field Effect Transistors into Si-lines. Novel activities in his group concern the use of nanotechnology for automotive applications.