Scholarly article on topic 'Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates'

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates Academic research paper on "Nano-technology"

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Academic research paper on topic "Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates"

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

Nan Y. Pacella,a z Mayank T. Bulsara,a Charlotte Drazek,b Eric Guiot,b and Eugene A. Fitzgerald®

aDepartment of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA

bSOITEC, Parc Technologique des Fontaines, Crolles Cedex, Bernin 38190, France

The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915° C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO2 and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0221507jss] All rights reserved.

Manuscript submitted March 24, 2015; revised manuscript received April 24, 2015. Published May 7, 2015.

Monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal-oxide semiconductor (CMOS) enables advanced circuits with increased performance and functionality and promotes system-level miniaturization. The Silicon on Lattice Engineered Substrate (SOLES) platform is a Si wafer with embedded III-V template layer that has been developed for III-V/Si integration and is illustrated in Fig. 1.1,2 A silicon-on-insulator (SOI) layer on top provides the high quality substrate necessary for CMOS device processing whereas the III-V template acts as a seed layer for epitaxial III-V device growth. This III-V template layer is accessed by etching windows through the top Si and buried insulator layers. The SOLES substrate structure is designed to add functionality to a CMOS platform while maintaining compatibility with Si processing infrastructure. Exposure to the III-V template layer is avoided until the CMOS process sequence is complete and the III-V device epitaxy and processing can be treated in a similar manner to backend metal processing.

Much of the development effort for the SOLES substrate platform to date has been on the Ge SOLES substrate, in which Ge forms the embedded III-V template layer, due to the current acceptance of Ge in Si facilities and near lattice match to GaAs. Ge SOLES wafers were first demonstrated by Dohrman et al. by transferring a Si device layer onto an epitaxial Ge template layer on Si, which was established using a SixGe1-x graded buffer.1 Subsequently, layer transfer processes with bulk Ge substrates led to the development of Ge SOLES wafers with a Ge-on-oxide (Ge-OI) layer as the III-V template, as demonstrated by Letertre.3 These Ge-OI SOLES wafers were successfully processed for demonstration of differential amplifiers consisting of monolithi-cally integrated InP heterojunction bipolar transistors (HBT) and Si CMOS.4 Although successfully modified, design of the CMOS process flow was limited due to the low melting point of Ge (938°C). Furthermore the integration of InP HBT layers required the introduction of InxAl1-xAs metamorphic buffer layers, which increases process complexity and impedes thermal heat extraction through the back side of the Si substrate. Therefore, direct incorporation of InP into the SOLES wafers is desirable. The high melting point of InP (1062°C) and its complete compatibility with InP HBT structures offers the potential for Si/III-V device integration process design flexibility. The elimination of compositional grading between the template layer and

zE-mail: nanyang@alum.mit.edu

device layer would offer the potential for processing simplicity and better thermal heat extraction efficiency.

The origin and characteristics of the III-V template layer must be carefully considered. The best quality III-V template layers come from bulk III-V or Ge substrates. However, these bulk substrates are limited in their scalability due to the availability and/or expense of larger wafer sizes and thermal mismatch between the III-V materials and Si substrates. Epitaxial deposition of template layer films grown on Si substrates enables, in principle, scaling to any wafer size available for Si wafers and ensures thermal mismatch compatibility with Si handle wafers for subsequent wafer bonding and layer transfer.

Thus, two versions of InP SOLES substrates with different constructions are demonstrated here for the first time, both utilizing InP template layers epitaxially grown on Si. In the first structure, the InP template is only flanked by SiO2 on one side. A more advanced InP-OI SOLES, which parallels the Ge-OI SOLES structure in that the InP is sandwiched between two SiO2 layers, was then created.3 Finally, properties of the various Ge and InP SOLES structures were studied in an effort to provide guidelines for process design and further elucidate paths for enabling more advanced SOLES wafers with even greater integration capability and flexibility.

Ge-Based SOLES

Experimental.— The Ge-OI SOLES wafers are fabricated with the specifications and processing conditions listed in Table I. In all cases, the SiO2 immediately beneath the top Si layer is thermal oxide. For structures A, B and C, a plasma-enhanced chemical vapor deposition (PECVD) SiO2 layer is present on top of the Ge. A key processing step for PECVD oxide is that it is typically densified at high

Si Device Layer BOX

Si substrate

Figure 1. Schematic of the Silicon on Lattice Engineered Substrate (SOLES) platform. A III-V template layer is embedded in a Si wafer and separated from the top Si device layer with a buried silicon dioxide (BOX) dielectric layer.

Table I. Specifications and fabrication conditions for Ge-OI SOLES structures investigated in this work.

Sample

Wafer Size (mm) 150 200 200 200

SOLES Layer Structure Target Thicknesses

Si (nm) 430 550 700 700

Thermal SiO2, Top BOX (nm) 500 900 170 235

PECVD SiO2, Top BOX (nm) 450 100 100 n/a

Ge (nm) 100 100 100 100

PECVD SiO2, Bottom BOX (nm) 200 100 100 100

Thermal SiO2, Bottom BOX (nm) 200 100 100 100

Top BOX Layer Processing Conditions

Thermal SiO2 Deposition Temperature n/a 1100°C 950°C 950°C

Bond Interface SiO2-SiO2 SiO2-SiO2 SiO2-SiO2 SiO2-Ge

Bonding Process Standard Standard Plasma- activated Plasma- activated

temperatures and planarized prior to bonding. Note that in Structure B, the thermal oxide is thinner and grown at higher temperature than that for structures C and D. In addition, bonding surfaces of wafers C and D were plasma activated prior to bonding.

Allowable thermal budgets for device processing were determined for the Ge SOLES samples. The wafers were cleaved into pieces and annealed in a tube furnace in N2 ambient for 8.5 hours at temperatures up to 940 ± 5°C. This duration was chosen to be consistent with a safe thermal budget devised for the previous implementation of monolith-ically integrated InP HBT and Si CMOS, reported by Yang et al.5 Plan-view optical microscopy (Nomarski) and cross sectional transmission electron microscopy (TEM) were used to confirm structural changes in the wafers after annealing whereas secondary ion mass spectroscopy (SIMS) was performed in order to determine Ge diffusion profiles in the substrates. TEM samples were made by cleaving the wafers into small pieces, manually polishing with silicon carbide lapping film of successively finer grit size, followed by ion milling at a glancing angle of 15o. A JEOL 2011 High Contrast Digital TEM is used in this work.

Results: Structural stability and diffusion in Ge-OI SOLES.— Thermal budget considerations are extremely important for SOLES substrates. TEM images of Ge-OI SOLES Structure A, as-fabricated and after 8.5 h anneal at progressively higher temperatures, are shown in Fig. 2, top.5 At 940 ± 5°C, Ge melting, agglomeration and film de-lamination can clearly be seen. For Ge-OI SOLES wafers annealed at 920 ± 5°C, neither TEM nor Nomarski reveals any structural change in the buried Ge layer. Thus, 915° C was determined to be a conservative safe thermal budget for Ge-OI SOLES structurally.

In addition to major structural changes, Ge diffusion through the SOLES wafers was considered. SIMS concentration profiles of Ge in Ge-OI SOLES after 920 ± 5°C anneal are shown in Fig. 3. There is progressive Ge diffusion through the buried SiO2 layers and Ge accumulation at the bond interfaces and heterointerfaces.

For Structure A, Ge concentrations after annealing according to the thermal budget of the CMOS process utilized for the integrated InP HBT previously reported by Liu et al. and Yang et al.4,5 is shown. Though some Ge diffusion through the BOX does occur, the modified thermal budget successfully curtails the extent of this diffusion and eliminates high Ge accumulation levels at the Si/SiO2 interface.5 For Structures B, C and D, the Ge profile in the as-fabricated wafers are shown in Fig. 3, together with the Ge diffusion profile after 805 ± 5°C, 855 ± 5°C and 920 ± 5°C. The location of Si/SiO2 and SiO2/SiO2 interfaces can be easily identified by Ge spikes.

Discussion: Diffusion in Ge-OI SOLES.— As shown in Fig. 3, any Ge species in the Si device layer of the Ge-OI SOLES is below the detection limits of SIMS. However, the high Ge concentrations at the Si/SiO2 interface is of some concern to CMOS devices on the SOI. Ge atoms create interface states at Si/SiO2 interfaces and would be especially critical if the most advanced fully-depleted-SOI CMOS

devices were to be built on this Si layer. Additional analysis of Ge diffusion in the SOLES structure provides a better understanding of how to limit it.

In Ge SOLES structures B and C, with progressively higher annealing temperature, 1) the total planar density of diffused Ge atoms, NGe (#Ge atoms/cm2), at the SiO2/SiO2 bond interface remains approximately constant, 2) an accumulation of Ge in the thermal oxide is accompanied by a corresponding depletion of Ge in the PECVD oxide and 3) Ge progressively accumulates at the Si/SiO2 interface at higher temperatures. Further, integration under the SIMS curve reveals that the total concentration of diffused Ge remains approximately constant in Structures B, C and D; however, there is an increase in total Ge incorporation in the BOX layer of Structure A.

For Structures B, C and D, the constant total NGe in the BOX indicates that annealing causes a redistribution of Ge species already present in the oxide layer after SOLES wafer fabrication. Additional Ge diffusion from the bulk layer is too low to be detected in SIMS.

Figure 2. Cross-sectional TEM images of Ge-OI SOLES Structure A (a) as-fabricated, (b) after 920 ± 5°C anneal and (c) 940 ± 5°C anneal, adapted from,5 and Structures (d) B, (e) C and (f) D after 920 ± 5°C 8.5 hour anneal. All images are taken using the [011] zone axis. The approximate positions of the bond interfaces are indicated by the white lines.

Figure 3. Ge concentration profiles in Ge-OI SOLES structures from secondary ion mass spectroscopy (SIMS). Overlaid on each plot is the SOLES structure, with bond interfaces indicated by dashed lines. (a) In Structure A, Ge concentration profile after 920 ± 5°C, 8.5 hour anneal ( ) and after representative CMOS thermal budget ( ) are shown. (b, c, d) In Structures B through D, Ge concentration profiles in as-fabricated wafers ( ■■) and after 805 ± 5°C ( _ ), 855 ± 5°C ( ) and 920 ± 5°C ( ) anneal are shown.

The assumption that there is no substantial Ge diffusion from the bulk enables modeling of Ge diffusivity in the thermal SiO2 as a 1-D Gaussian distribution and for diffusivity to be extracted. The diffusivities in Structures B and C vary between 2e-15 and 3e-14 cm2/s between 800°C and 920°C and are shown as a function of temperature in Fig. 4. From this data, a diffusion coefficient, Do = 5.6e-7 cm2/s and activation energy, EA = 1.7 eV was extracted for Ge diffusion in Structure B. The diffusivity of Ge in Structure C is an order of magnitude lower than in Structure B.

Diffusion in SiO2 is often strongly affected by the impurities in, and bonding structure of, the SiO2 matrix.^11 The activation energy

Figure 4. Ge diffusivity, D, in thermal SiO2 as a function of temperature for SOLES Structures B (♦) and C (0).

of 1.7 eV found in this work is consistent with oxygen-enhanced Ge diffusion as a Ge-O complex, which has EA = 0.95 eV and >1.55 eV for Ge diffusion in 50nm or 100nm of unencapsulated SiO2 in O2 ambient.7-10

Oxygen-enhanced Ge diffusion was understood by Beyer and von Borany as the diffusion of a Ge-O complex.8 Ge bonds with oxygen to create a Ge-O complex which enters the SiO2 matrix and forms an oxygen-deficient center (ODC) which diffuses through the rapid breaking and re-forming of bonds at high temperatures. Through this bond-hopping mechanism, Ge diffuses much faster, with lower activation energy, than in its "elemental" form, in which is must diffuse through the free volume of SiO2. Two studies have found diffusivity below 3e-19 cm2/s at 920°C and EA = 6.6 eV12 and EA = 3.9 eV13 for Ge diffusion without the aid of oxygen, which corresponds to diffusion lengths of less than 9.6 A. Note that Ge diffusivity values in the SOLES thermal oxide layers are also orders of magnitude lower than the 2e-8 cm2/s diffusivity at 920°C previously found in PECVD SiO2, which has high H2 concentration.11

At the SiO2/SiO2 bond interface, a high concentration of Ge species accumulates. This is likely due to the high density of dangling bonds, greater free volume at this location and -O-H-O- bridges formed through the hydrophilic wafer bonding process. The fast diffusing Ge-O species can easily pick up additional oxygen to form immobile GeO27-10,14-16 After all of the additional oxygen groups at the bond interface react to form GeO2, Ge concentration at that interface remains constant.

At the Si/SiO2 interface, there is a very strong driving force for Ge-O to precipitate from the oxide by interacting with a Si-O group at the interface and form elemental Ge, GeO + SiO ^ SiO2 + Ge.8

Because it is a fully miscible system, this Ge then diffuses into the Si, forming SiGe.17 Ge diffusivity in Si is 2.6e-18 cm2/s at 920°C,13 which results in a diffusion depth of 57A after an 8.5 hour anneal. Thus, it appears as a spike in the SIMS concentration profile. (Note that the highest Ge accumulation shown in the SIMS data in Fig. 3 is 2.9e19 cm-3, for Structure B annealed at 920°C. This concentration corresponds to a Ge concentration of less than 0.06%. The small amount of strain presented by 0.06% Ge is easily accommodated and is therefore inconsequential from a structural perspective but presents a potential electrical challenge to CMOS devices on the SOI.)

One method of mitigating Ge diffusion is by incorporating higher quality oxide into the SOLES structure. The thermal oxide in SOLES Structure C is grown at lower temperature and is therefore of higher quality, with lower OH incorporation18 and higher density.19,20 Ge diffusivity in Structure C is indeed an order of magnitude lower than that in Structure B.

In Structure D, thermal oxide was bonded directly to Ge without an intervening PECVD oxide layer. With the lower quality PECVD oxide eliminated from the structure, the total concentration of diffused Ge is much lower than in Samples A, B, and C, which contain PECVD oxide. The Ge that does incorporate in the BOX may be a result of plasma activation of the Ge surface prior to wafer bonding, which creates a thin layer of GeO2 and GeO on the surface of the Ge.21

Structure A is the only Ge SOLES structure investigated in this work where NGe in the BOX does not remain constant as a function of anneal temperature. The thicker PECVD SiO2 and continuous incorporation of Ge from the bulk renders the diffusion behavior much more complex. Ge-O concentration in the PECVD oxide has not saturated during the wafer fabrication process. Thus, after annealing, additional Ge from the bulk could still enter the SiO2 matrix and form fast-diffusing Ge-O complexes, increasing total Ge in the oxide. This data suggests that the quality and history of the PECVD SiO2 dictate the initial Ge species concentrations in the SOLES structure and the subsequent Ge concentration profiles.

InP-Based SOLES

Experimental.— In order to create InP-based SOLES, InP-on-Si handle wafers are fabricated by first growing InP thin films on 150 mm Si wafers, 6° offcut toward the {111} plane with an Aixtron/Thomas Swan metallorganic chemical vapor deposition (MOCVD) reactor designed with the capability of growing Group IV and III-V films in the same chamber. The Si wafers were cleaned prior to InP epitaxy with 10 minute piranha etch followed by the removal of native oxide with a 10:1 H2O:48% HF. First, a homoepitaxial Si buffer layer was grown in an H2 ambient at 825°C using silane (SiH4) as the precursor. This homoepitaxial layer is followed by ~50 nm Ge and ~100 nm GaAs interlayers, grown at 350°C and 650°C respectively under N2 ambient, which promoted better InP film morphology. Precursors for Ge and GaAs film growth were germane (GeH4), trimethylgallium (TMGa) and arsine (AsH3). InP was then grown using a two-step growth procedure which included a low temperature initiation layer and higher temperature bulk growth layer. This growth was performed using trimethylindium (TMI) and phosphine (PH3), again under N2 ambient. Finally, the films were thermal cycled to improve film quality.

The optimal InP film growth conditions to achieve good film quality were determined using design of experiment (DOE) methodology with initiation layer V/III precursor ratio, initiation layer thickness, initiation layer growth temperature, final growth temperature and thermal cycle temperature as the variables. The optimal quality InP film growth sequence ultimately used in this work consisted of a 100 A InP initiation layer grown at 400°C with a V/III ratio of 2000, followed by raising the temperature to 600°C for deposition of a thicker "bulk" InP layer. In order to further improve film quality, samples with progressively greater InP film thickness were grown, encapsulated with SiO2 and then thermal cycled four (4) times between 250°C and 800°C in a tube furnace under N2 ambient, as recommended by Hayafuji et al.22 Both the thicker film and thermal cycling increases the probability

Figure 5. Schematic of fabrication sequence for InP/Si SOLES and InP-OI SOLES. InP/Si and InP-OI designate the structure of the buried InP layer. (1) PECVD SiO2 is deposited on the InP/Si donor wafer, densified and planarized. (2) This substrate is then bonded to a thermally oxidized SOI donor wafer. To create InP/Si SOLES, (3a) the Si and SiO2 from the SOI donor wafer are removed. To create InP-OI SOLES, (3b) the Si substrate and Ge and GaAs initiation layers from the InP/Si donor wafer are removed. PECVD SiO2 is deposited on the back side of the InP, densified and planarized. (4) This wafer is then bonded to a thermally oxidized Si handle wafer and (5) finally, Si and SiO2 layers from the SOI donor wafer are removed.

of dislocation interaction and annihilation. Finally, film quality was characterized using both cross-sectional and plan-view TEM on the [011] zone axis and [220] as well as the full-width at half-maximum (FWHM) of the InP rocking o>-2© curves in X-ray diffraction (XRD).

InP-based SOLES wafers were then fabricated through wafer bonding and layer transfer. An oxide-oxide hydrophilic bond was chosen for ease of implementation and to mirror the process used to create Ge-based SOLES.1,3 Two versions of InP SOLES were fabricated and designated in this work by the buried InP template structure as InP-on-Si SOLES and InP-OI SOLES. The fabrication processes are shown in Fig. 5.

For both structures, the fabrication sequence started with (1) PECVD deposition of SiO2 on an InP-on-Si handle wafer using an STS PECVD, oxide densification at 700° C in a tube furnace under N2 ambient and planarization using CMP to achieve surface conditions necessary for bonding. (2) This InP-on-Si handle wafer was then bonded to a thermally oxidized SOI wafer, creating a BOX layer. Bond strengthening anneals were then performed at 800° C in a tube furnace in N2 ambient. To create the InP-on-Si SOLES structure, (3a) the Si and SiO2 from the SOI donor wafer was removed using mechanical grinding and KOH wet chemical etching.

Fabrication of the InP-OI SOLES was more complex. After the first bond-strengthening anneal, (3b) the Si substrate and GaAs and Ge adhesion layers from the InP-on-Si wafer were removed using api-ranha etch, after which a PECVD oxide was deposited on the exposed InP surface. This PECVD oxide film was densified and planarized to create a smooth bonding surface. (4) This structure was bonded to a thermally oxidized Si handle wafer to create a second BOX layer. At this point, (5) the Si substrate and SiO2 from the SOI wafer were

Figure 6. Planview TEM images of InP-on-Si films with InP film thickness of (a) 1.85um, (b) 3.9um and (c) 4.5um after 800°C thermal cycle taken in bright field, using [220] diffraction condition. (d) FWHM (■) and TDD (♦) for these films. All TEM images share the same scale bar.

finally removed through a combination of mechanical grind and KOH wet chemical etch to create the final InP-OI SOLES.

Similar to the Ge SOLES structures described above, allowable thermal budgets were determined for the InP based SOLES structures. InP-on-Si SOLES samples were cleaved into pieces and only annealed at temperatures up to 860°C for 4 hours. The more advanced InP-OI SOLES structures underwent longer anneals for 8.5 hours at temperatures up to 940 ± 5°C to mirror Ge-OI SOLES. Nomarski, cross sectional TEM and SIMS were performed to understand the physical properties.

Results: InP SOLES demonstration and thermal stability.— Using the InP-on-Si growth procedures described above, InP films with FWHM of 207 arcsec from XRD of the InP peak and TDD of 9.5 ± 0.3E7 cm-2 was achieved for 4.5 |xm thick InP films, as shown in Fig. 6. TDD was calculated by counting dislocations captured in ten (10) bright field PVTEM images taken in the [220] beam condition. The area of each image is approximately 20 um. Lower thickness films exhibited higher dislocation density and more stacking faults.

InP-on-Si SOLES and InP-OI SOLES were both successfully made using wafer bonding and layer transfer. A photograph and cross-sectional TEM images of the InP-on-Si SOLES substrate, before final SiO2 etch, is shown in Fig. 7. Note that 1.85 |im InP films are used for the InP SOLES demonstration here and a high density of dislocations can be seen in the InP film. The bond interface is indicated by the white lines.

The InP-on-Si SOLES wafers have thermal stability which is far below that required for Si CMOS processing. Cross sectional TEM images of these Ge and GaAs buried layers after annealing at 810° C and 860°C are presented in Fig. 8. At the GaAs/InP interface, a distinct new layer, bounded by a dislocation array at either end and indicated by the white lines in Figs. 8a and 8b, is formed. With progressively higher temperature, the thickness of this layer in between the dislocation array also grows. Further, in the wafer annealed at 860°C, a much more extensive network of dislocations which extends greater than 500nm into the Si substrate in some areas can be seen.

For purposes of this work, the stability of InP SOLES is improved by developing the InP-OI SOLES structure. TEM and optical microscope images of InP-OI SOLES wafers after progressively higher

Figure 7. (a) Photograph of InP-on-Si SOLES wafer. The SiO2 from the SOI donor wafer is still intact. Cross sectional TEM images of InP-on-Si SOLES structure (b) on [011] zone axis and (c) in the [220] diffraction condition to highlight the dislocation network. The bond interfaces is indicated by the white line.

temperature 8.5 hour thermal anneal are shown in Fig. 9. Though some blisters can be seen in the Nomarski images (even in the as-fabricated wafers), after extended 800 ± 5°C anneal, there were no observable changes in their density or size. At higher temperatures, however, these blisters grew and led to areas of local film delamination.

Despite a slight increase in blister density, the InP-OI SOLES structure is largely robust up to 850 ± 5°C with minimal detectable structural changes in the InP film. Between 850 ± 5°C and 915 ± 5°C, significant changes do occur. Though some parts of the SOLES structure remain intact, there are also portions of the sample where the continuous InP interlayer has transformed to form nanoparticles in the SiO2. At even higher anneal temperatures, intact InP layers become increasingly difficult to find, even on a TEM scale. Nanoparticle

Figure 8. Cross-sectional TEM images of Ge and GaAs initiation layers in the InP-on-Si structure after (a) 810°C and (b and c) 860°C anneal for 4 hours. Images are taken in bright field using the [220] diffraction condition to better highlight dislocations.

Figure 9. Cross-sectional TEM (a-e) and plan view Nomarski microscope (f-j) images of InP-OI SOLES as-fabricated (a and f) and after 800 ± 5°C (b and g), 850 ± 5°C (c and h), 915 ± 5°C (d and i) and 1000 ± 5°C (e and j) 8.5 hour anneals. TEM images are taken on the [011] zone axis.

formation can be seen in some areas; InP simply de-bonds from the SiO2 in others (not shown).

In addition to structural integrity, diffusion of In and P up to the Si device layer is also considered. For InP-OI SOLES, SIMS concentration profiles of In and P after extended 850 ± 5°C anneal and of In after 915 ± 5°C anneal are shown in Fig. 10. Extensive In diffusion is seen throughout the SiO2 film but there is no sign of P diffusion. A few characteristics of these SIMS scans for InP-OI SOLES should be noted. Due to sample charging during the SIMS scan (from the thick SiO2 layer); the Si substrates are removed prior to acquiring SIMS data. Indium concentration data in the top Si layer is captured from a front-side scan for the 915 ± 5°C sample, whereas the same data for the 850 ± 5°C sample is captured from a back side scan. In both cases, In is below the detection limit of SIMS. Because back side scans were performed for these films, the new surface of the 915 ± 5°C annealed sample was positioned at ~3.5 |xm whereas the new surface of the 850 ± 5°C annealed sample was positioned at ~5 |im. The decrease in Indium concentration at each of these positions may be a surface artifact.

Discussion: Structural stability of InP-on-Si SOLES.— The dislocation arrays present at the GaAs/InP and Si/Ge interfaces of the InP-on-Si SOLES structure shown in Fig. 8 suggest that progressive interdiffusion of the GaAs layer with InP and of the Ge layer with Si is possible. At the GaAs/InP interface, there is an unidentified layer bounded by two dislocation arrays. It is possible that this intermediate layer contains all four elements (In, Ga, As, and P) as reported by Jin-Phillipp et al. for a bonded InP/GaAs interface.23 The clear defi-

nition of the new layer may be a result of the miscibility gap in the quaternary system, as shown by Cohen.24

With higher thermal budget anneals, the dense dislocation network between Ge and Si also becomes progressively thicker, extending both up into what was originally the Ge film and down into the Si substrate. This dislocation movement suggests Ge-Si interdiffusion and strain relaxation over a larger thickness. No distinct interfacial layer is seen between Ge and Si, consistent with the complete miscibility of this materials system.

Given that this highest anneal temperature used in this work for the InP-on-Si substrate is close to the eutectic temperature of the GaAs-Ge system, it is possible that localized melting may have given rise to the interaction between all of the layers at 860°C, as shown in Fig. 8c. Additional work such as energy dispersive spectroscopy (EDS) or selective area diffraction (SAD) would further confirm this hypothesis.

Discussion: Structural stability and diffusion in InP-OI SOLES.— Nomarski revealed the only macro-scale surface defect in the InP-OI SOLES wafer structure after annealing at progressively higher temperatures to be an increase in blisters, as shown in Fig. 9. One hypothesis for the source of these blisters is that they arise from imperfect wafer bonding, possibly due to contamination at the bond interface. However, the true origin of these blisters requires further study and would best be understood through TEM or scanning electron microscopy (SEM) images of samples prepared using focused ion-beam (FIB) to target the precise location of the blister.

On a local scale, the InP-OI SOLES structure was largely robust up to 850 ± 5°C with no detectable structural change in TEM, as seen in Fig. 9c. Between 850 ± 5°C and 915 ± 5°C, however, there are portions of the sample where InP forms nanoparticles in the lower SiO2 layer, Fig. 9d. At even higher temperatures, the effect is more catastrophic, as seen in Fig. 9e. The spatial separation of In and P shown in the SIMS data in Fig. 10 may elucidate the mechanism for this nanoparticle formation.

Indium diffusion throughout the SiO2 layer leaves a high concentration of P near the InP/SiO2 interface. The excess P can incorporate into the Si sites of the SiO2 network and form P2O5. Although the precise configuration of P incorporation in the SiO2 matrix needs to be confirmed, a P2O5 structure would be consistent with both the lack of P diffusion and the anomalous melting and nanoparticle formation. With reference to the former, the P2O5 structure is relatively immobile in SiO2.6 With reference to the latter, SiO2-P2O5 has a eutectic

Figure 10. Concentration profiles of In and P in InP-OI SOLES after extended 850 ± 5°C, 8.5 hour anneal ( ) and of In after 915 ± 5°C, 8.5 hour anneal ( ).

temperature at approximately 850°C (and 20% P2O5),25,26 far below the melting point of either SiO2 or InP alone and corresponding to the lowest temperature at which nanoparticle formation is seen in this work. Thus, extreme care must be taken when considering wafer fabrication thermal budgets for the current InP-OI SOLES structures.

In contrast to the low P diffusion, the SIMS data in Fig. 10 reveals that indium diffusivity in the buried oxide layers of the InP-OI SOLES structure is extremely high. Similar to Ge, indium diffusion in SiO2 has been proposed to occur via slow In+ ion diffusion and fast oxygen-enhanced diffusion mechanisms.6 Oxygen-enhanced In diffusivities have been found to be on the order of 1e-13 cm2/s in thermal oxide at temperatures relevant to this work.27,28 For the InP-OI SOLES wafers demonstrated here, since a majority of the BOX layer is comprised of PECVD SiO2, a fast diffusion mechanism such as oxygen-enhanced diffusion is very likely. Just as higher Ge diffusivity had been found in PECVD oxide as compared against thermal oxide, very high In diffusivity is present in the PECVD oxide in this InP-OI SOLES structure.

Finally note that indium accumulates at the highly imperfect SiO2/SiO2 bond interface, similar to Ge, but there is no indium peak at the Si-SiO2 interface. Given indium's solid solubility in Si of only ~1e18cm-3,29 and segregation coefficient of between ~0.1 and0.001 in this temperature range studied here,28,30 indium remains in the SiO2 over Si. The lack of In diffusion into the Si device layer is advantageous for the CMOS devices which would be processed on this Si layer. However, the high In levels in the BOX may still make the InP-OI SOLES integration platform a challenge for integrating fully-depleted SOI CMOS devices.

Conclusions

SOLES substrates present a viable platform for integrating Si CMOS and III-V compound semiconductor devices. However, due to the stringent requirements demanded of SOLES substrates, careful design of wafer fabrication procedures and device processing steps is necessary. Two versions of InP SOLES wafers are demonstrated through bonding of silicon, SOI and InP-on-Si wafers grown using a two-step growth method. The allowable processing budgets of these InP SOLES substrates are studied in detail and compared with previously fabricated Ge SOLES substrates in order to elucidate the optimal methods of fabricating SOLES wafer structures.

The simplest fabrication process for creating a SOLES substrate entails a single bonding and layer transfer step. A Si device layer is transferred onto a III-V template supported on Si, as in Ge/SiGe SOLES1 or InP-on-Si SOLES. For these SOLES substrates, it is the buried layers between the III-V template and Si substrate that impose the most severe thermal budget constraints to subsequent device processing.

It is therefore advantageous to simplify the final SOLES structure by using a double layer transfer process to create SOLES structures with two BOX layers. Replacing the layers beneath the III-V template with SiO2 also has the advantage of eliminating the III-V/group IV interface (for InP-on-Si SOLES substrates) and improving isolation schemes.

Finally, the quality of the two BOX layers must also be optimized in order to limit diffusion of the III-V template materials and improve allowable processing thermal budgets. For Ge-OI SOLES high quality oxide has been shown here to mitigate Ge diffusion through the SiO2 matrix and accumulation near the Si/SiO2 interface. Further, incorporation of SiNx diffusion barriers were previously demonstrated.5 For InP-OI SOLES substrates, the effect of higher quality oxides and diffusion barriers in limiting the spatial separation between In and P and improving thermal stability should be explored. Anomalous melting of the InP layer below the expected melting temperature of InP should also be better understood. Finally, the thermal budget of

CMOS processing steps should also be designed to avoid melting of and minimize diffusion of the III-V template material.

Acknowledgments

This work was funded by the DARPA COSMOS program, ONR contract number N00014-07-C-0629, and made use of MIT MTL and CMSE facilities.

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