Scholarly article on topic 'Design of Multiplier-less FIR filters with Simultaneously Variable Bandwidth and Fractional Delay'

Design of Multiplier-less FIR filters with Simultaneously Variable Bandwidth and Fractional Delay Academic research paper on "Electrical engineering, electronic engineering, information engineering"

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{"Variable bandwidth filter" / "Variable fractional delay filter" / "ABC optimization" / "Farrow structures" / Multiplier-less}

Abstract of research paper on Electrical engineering, electronic engineering, information engineering, author of scientific article — Aravind Illa, Nisha Haridas, Elizabeth Elias

Abstract Low complexity and reconfigurability are the key features in emerging communication applications in order to support multi-standards and operation modes. To obtain these features, an efficient implementation of finite impulse response (FIR) filter, with Variable Bandwidth and Fractional Delay, is proposed in this paper. The reduction in the implementation complexity is achieved by converting the continuous filter coefficients to signed power of two (SPT) space. This may lead to performance degradation. Hence, in this paper, Artificial Bee Colony (ABC) optimization is deployed for finding the near optimal solution in the discrete space.

Academic research paper on topic "Design of Multiplier-less FIR filters with Simultaneously Variable Bandwidth and Fractional Delay"

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Engineering Science and Technology, an International Journal ■■ (2016) I

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Engineering Science and Technology, an International Journal

journal homepage: http://www.elsevier.com/locate/jestch

Full Length Article

Design of Multiplier-less FIR filters with Simultaneously Variable Bandwidth and Fractional Delay

Aravind Illa, Nisha Haridas *, Elizabeth Elias

Department of Electronics and Communication Engineering, National Institute of Technology Calicut, Kerala, India

ARTICLE INFO

Article history: Received 1 October 2015 Received in revised form 28 December 2015 Accepted 28 December 2015 Available online

Keywords:

Variable bandwidth filter Variable fractional delay filter ABC optimization Farrow structures Multiplier-less

ABSTRACT

Low complexity and reconfigurability are the key features in emerging communication applications in order to support multi-standards and operation modes. To obtain these features, an efficient implementation of finite impulse response (FIR) filter, with Variable Bandwidth and Fractional Delay, is proposed in this paper. The reduction in the implementation complexity is achieved by converting the continuous filter coefficients to signed power of two (SPT) space. This may lead to performance degradation. Hence, in this paper, Artificial Bee Colony (ABC) optimization is deployed for finding the near optimal solution in the discrete space.

Copyright © 2016, The Authors. Production and hosting by Elsevier B.V. on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/

licenses/by-nc-nd/4.0/).

1. Introduction

Applications such as spectrum sharing radios and emerging communication systems, which provide multi-modes, multi-standards and multi-services, require variable bandwidth filters [1-3]. In order to support various operating modes variable fractional delay filters are also considered. In the literature, design of some variable digital filters are discussed in References 4-6.

In this paper, the design method proposed in Reference 4 is considered. The overall filter structure is shown in Fig. 1. The impulse response is a two-dimensional polynomial in the bandwidth and fractional delay parameters. In this structure, the overall transfer function is a weighted linear combination of fixed linear-phase FIR subfilters cascaded with pre-designed farrow structure based variable fractional delay. Variability is achieved by few adjustable parameters determined for the bandwidth and delay requirements. By utilizing the Farrow structures, the impulse response of the filter based on polynomial realization supports the offline design of fixed FIR subfilters and simple online update of variable multipliers. Thus, updating is simple and is reported to have significant savings in the number of multiplications and additions compared to the previous polynomial based realizations.

A further reduction in complexity is proposed in this paper to represent the infinite precision coefficients of the filters by finite

* Corresponding author. Tel.: +919895465581. E-mail address: nisha_p120093ec@nitc.ac.in (N. Haridas). Peer review under responsibility of Karabuk University.

precision in the SPT space, by making use of the Canonic Sign Digit (CSD) representation of the filter coefficients. There are various methods for minimizing coefficient complexity in literature. Coefficient complexity reduction includes reducing the coefficient word length and coefficient representation using a limited number of signed power-of-two (SPT) terms. Signed power-of-two representation uses three-valued digits instead of binary digits, 0,1 and -1. Canonic signed digit (CSD) is the special case of signed-digit power-of-two, with minimal number of non-zero digits. CSD has minimal number of non-zeros. The multiplier components consume major power and area of a filter, and thus these are replaced by shifters and adders. This may result in the performance degradation of the filter response. Hence, suitable optimization algorithms are needed to improve the performances of the filter [7-10]. Since the search space contains integers, the classical gradient-based optimization algorithms cannot be used [11]. In this paper, ABC optimization algorithm is used because it is reported that ABC algorithms are especially useful for finding near optimal solutions in multimodal and multi-dimensional objective problems and can be tailor made to suit the problem considered [7,9,12]. Multiplier-less design of FIR filter with variable bandwidth and variable delay with the coefficients synthesized in the CSD form using modified meta-heuristic algorithm is hitherto not reported in the literature.

The paper is organized as follows. Section 2 gives an overview of variable digital filters. Section 3 gives a brief introduction of CSD representation and ABC algorithm. Section 4 gives the design of variable digital filter using ABC optimization. The design example and discussion on results are given in Section 5 and Section 6 respectively. Section 7 concludes the paper.

http://dx.doi.org/10.1016/jjestch.2015.12.010

2215-0986/Copyright © 2016, The Authors. Production and hosting by Elsevier B.V. on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

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Fig. 2. The realization of G(z, d) [4].

Fig. 1. The variable digital filter [4].

2. Review of variable digital filters

The desired frequency response of FIR filters with simultaneously variable bandwidth and fractional delay, DH (jwT, b, d) is given by Reference 4. It is based on Farrow structure [13], which is widely used as variable fractional delay filters. Applications of this structure are detailed in Reference 14.

DH (aT,b, d)

eiaT(NH'2+d> aT e[0,b -A] 0, aT e[b + A, n]

Here, d and b are adjustable fractional delay and adjustable bandwidth parameters, respectively, d e [-12,12 and b e [b, bu], where bu, and bi respectively are the upper and lower bounds of the adjustable bandwidth parameter b. For each pair of values of b and d, the variable filter corresponds to a lowpass filter with a fractional delay of NH/2 + d in the passband, where NH is the order of the filter. This desired function can be approximated using a transfer function H(z, b, d) in a cascade form [4] of order NH = NF + NG, given by,

H (z, b, d ) = F (z, b )G (z, d )

where, F(z, b) is a variable bandwidth filter given by Eq. (3), which approximates the desired frequency response in Eq. (4), and b0 =(bt + bu)/2. Similarly, G(z, d) is a variable delay filter given by Eq. (5), which approximates the desired frequency response in Eq. (6).

F (z,b ) = £(b -b.

0 )PFp (z )

Df (aT, b )

eiaTNF/2 aT e[0,b -A] 0, aT e[b + A, n]

G (z, d) = ^dkGk (z)

Dg (aT, d ) = eiaT (G¡2+d ) aT e[0, bu-A]

where NF and NG are the orders of sub-filters Fp(z) and Gk(z) respectively. The variable filter structure [4] is shown in Fig. 1 The filters Fp(z) and Gk(z) are fixed and are chosen to be linear phase FIR filters. The filters G(z, d) are chosen to have farrow structure and the realization is shown in Fig. 2. The transfer function of the variable digital filter is given by

H (z,b, d ) = £Fp (z)G (z, d )(b -b0

The modulus of error between the desired and approximated transfer function is given by

E (z,b, d) = H (z,b, d)-DH (z,b, d)

Hence, the design problem is reduced to the non-linear optimization problem, which has to minimize the complex error function E (z, w, d )|<5 in the region mT = [0, b-A]u[b + A, n] [4]. If the targeted approximation error Se is given, then the subfilter orders NF and Ng are estimated as in Eq. (9) and then rounded to the nearest even integers [4].

2nlog10 (105;; 3A

4nlogi0 (m2 ) 3(n- bu + A)

After finding an approximate order of subfilters in F(z) and G(z) from Eq. (9), the number of subfilters for each is to be determined. This is done by separately designing the VBW filter F(z, b) and the VFD filter G(z, d) to approximate the functions in Eqs. (4) and (6) respectively with allowable error 4. Finally, to find the exact subfilter order, at each combination of NF and NG close to the approximated values, VBW and VFD filters are designed using minimax algorithm. Johansson and Eghbali [4] designs the filter coefficients using minimax algorithm such that it approximates the ideal filter response with minimum error. The proposed method optimizes error as well as implementation complexity. This is achieved by constraining coefficients to be in canonic signed digit (CSD) space. This enables the filter to be implemented without multipliers and only using adders. Minimum possible number of adders, without compromising the passband and stopband characteristics, is selected by means of optimization (using an evolutionary algorithm - Artificial Bee Colony algorithm (ABC)).

3. Overview of CSD and ABC algorithm

The approximation of the infinite precision multiplier coefficients of the variable digital filter into the SPT number representations will give us great advantage in the reduction of the hardware complexity. In this paper, canonic signed digit representation is used. It is a special case of the signed power of two representation system [7,15].

3.1. Canonic signed digit representation

The CSD representation uses a digit set that is ternary and each digit may be either -1, 0, or +l. Adjacent CSD digits are never both non-zero, i.e., bj*bj = 0. This property implies that for an n-bit number, there are at most n/2 non-zero digits. Any infinite precision multiplier coefficient c can be represented using the CSD format as follows:

c =YPi 2R

where i is the word length of the CSD number and integer R represents a radix point in the range 0 < R < L. Besides, bi e (-1,0,1). Hence, by CSD representation, multipliers can be replaced by shifters

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Table 1

A typical entry of the look-up-table.

Index CSD representation Decimal equivalent Number of SPT terms

7726 001000-10010-10-101 0.4715 6

and adders. The number of partial product adders can be decided by the number of non-zero bits in the filter coefficient representation. Hence, reducing the number of non-zero bits in the filter coefficient representation will reduce the number of adders. CSD is a unique representation for a given filter coefficient, with minimum number of non-zero bits.

3.1.1. Encoding variables in the CSD space

In this paper, 16 bit CSD representation is considered to represent a decimal number, 14 bits are used for the fractional part and 2 bits are used for the integer part. A look-up-table with four fields is created, which contains index, CSD numbers, decimal equivalent and the number of non-zero SPT terms. A typical entry of the look-up-table is shown in Table 1.

Since the sub-filters are linear phase filters, only half of the symmetrical coefficients of the sub-filters of F(z, b) and G(z, d) are needed to be used. Then obtain the corresponding signed indexes on the look-up-table locations for the CSD equivalents of the extracted filter coefficients. The signed indexes are concatenated together to form an initial vector in the optimization problem.

3.2. ABC optimization

In Reference 16, the ABC algorithm is proved as an efficient optimization algorithm for finding out the potential solution for a multidimensional, multi-modal optimization problem. The food source represents the possible solution to the problem and the nectar quantity determines its fitness value. In ABC algorithm, the colony of artificial bees contains three categories of bees: employed bees, onlooker bees and scout bees. Employed bees find a food source within the neighborhood of the food source in their memory and determine the nectar quality. If a food source with a higher nectar amount is found, the employed bees memorize the new position of the food source and forget the old food source position, else the old food source position is retained. Employed bees share their information with the onlooker bees. An onlooker bee will wait in the dance area for making the decision to choose a food source based on the nectar amount. The food source containing the high nectar will have higher probability to get more number of onlooker bees. An employed bee whose food source has been abandoned becomes a scout and it will search randomly for a new food source.

4. Design of variable digital filter using ABC optimization

The rounding-off of the infinite precision coefficients of the subfilters F(z, b) and G(z, d) with restricted SPT terms will degrade the performances [17-19]. Hence, the main objective of the optimization problem is to minimize the error of approximation, defined in the frequency domain as follows

E (X ) = ||Dh (a)-Hc (ffl,X)|| (11)

where Hc is response of the variable digital filter whose sub-filter coefficients are in SPT terms and X represents an optimized vector encoded in the CSD space.

In order to reduce the number of non-zero SPT terms in the CSD space, an additional constraint has to be imposed on the objective function. If A(X) represents the average number of nonzero SPT

coefficients and Ab indicates the upper bound of A(X), then the objective function is defined as follows

O (X ) = a1E (X ) + a2Z (X ) (12)

where Z(X) = max (0, A (X)-Ab), a1 and a2 are the corresponding weights for E(X) and Z(X) respectively. The weights of the objective function in Eq. (12) are positive weighting coefficients and are selected considering the relative importance of each term in the optimization problem, by means of trial and error to meet the required filter specifications and minimum number of non-zero coefficients. The various phases involved in the ABC algorithm to minimize the objective function, are given below [7]. An illustration of the algorithm using flow chart is given in Fig. 3.

4.1. Initialization of food source

The CSD coefficients of the fixed subfilters in the variable digital filter are concatenated to generate the initial food source. Since all the subfilters Fp(z) and Gk(z) have linear phase, only half the number of coefficients need to be considered. The other food sources are generated by randomly perturbating the initial food source. In order to begin with a wider search space, the initial number of food sources is selected to be an integer multiple of the number of employed bees.

4.2. Prioritized enlisting of food source

The fitness values of the initial food sources are evaluated and the food sources with a high fitness value are passed on to the next phase. The number of these prioritized food sources is taken as the same as the number of employed bees.

4.3. Employed bee phase

Employed bees search for a new food source within the neighborhood position of the food source in the memory and evaluate their fitness value. The new food source in the neighborhood of the ith food source can be obtained by changing the randomly selected jth parameter value in the ith food source as in the equation given below

xt+1 = xt ( - xj)) (13)

where xt is the jth parameter of the ith food source, xij+1 is the jth parameter of the new food source at the neighborhood of the ith food source, $ is a random value in the range [-1,1], and j e[1, 2,...,D] and k e [l, 2,...,D] are randomly chosen indexes. D is the dimension of the food source. ® is randomly selected in the range [-1 1]. The random value taken in each iteration of the optimization algorithm is used to decide a new set of possible solutions for the ABC evolutionary algorithm. In order to prevent the new food source from crossing the boundaries of the look-up-table, the steps given below are to be followed.

if xjj+i <v,b, then xt+i = Vib if xij+i >vub, then xt+i = vub

where Vib and Vub are the lower and upper bounds, respectively, of a parameter in a food source. If the new food source has higher fitness value than the old food source, then the old food source is replaced by the new food source in the memory.

4.4. Onlooker bee phase

Onlooker bees evaluate the fitness value of the food source based on the information shared by the employed bees and then they select

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Fig. 3. Flow diagram of ABC algorithm.

the food source based on probability. The food source that contains high nectar amount will have higher probability to get more number of onlooker bees than the food source with lower nectar amount. The onlooker bees also modify the solution in their memory similar to the procedure followed by the employed bees.

4.5. Scout bee phase

This phase helps to carry out the random search. If there is no improvement in the fitness values after a fixed number of iterations, then that food source is abandoned. The scout bees will search randomly for a new food source. In this search process, the scout bees memorize the food source having the best fitness value among the entire randomly selected food sources.

4.6. Termination phase

The phases from 4.1 to 4.5 are repeated until the approximation error becomes less than the tolerance value specified or up to a predetermined number of iterations. After the termination, the solution vector having the best fitness value is taken and the CSD digits are decoded to obtain the optimum filter coefficients.

When the ternary encoding is used, dimension of the optimization problem is large. Also, restoration algorithms [12] are needed to bring the non-canonical bit strings resulting from various operations into the CSD format. From the practical point of view, the traditional approach to generate the CSD representation uses lookup table.

5. Design example

In this design example the specifications are as follows: b¡ = 0.22n,bu = 0.54n, A = 0.12n, 5 = 0.01. The method in Section 2

is followed by initially choosing an approximate order using Eq. (9). The final values of P, K, NF and NG are arrived at by means of minimax optimization techniques. For this example, these values are found as, P = 4, K = 3, NF=26 and NG = 6. For comparison purpose, the same specifications given in example 1 in Reference 4 are chosen here. Further b has 11 values evenly distributed between bi and bu and with 6 values of d evenly distributed between 0 and 1/2.

The parameters used in the ABC algorithm are 50 number of employed bees and 50 number of onlooker bees, perturbation rate is 0.001, dimension of food source is 80, with weights a1 = 1 and a2 = 0.0035. The running time for optimization is 1204 seconds obtained for 500 maximum iterations. The modulus of the frequency response and error for the filter with continuous coefficients, CSD rounded and ABC optimized coefficients are shown in Figs. 4, 5 and 6 respectively.

Figs. 4-6 illustrate the performance of the filter with and without multipliers in its implementation. The filter is initially designed for the given specification for variable bandwidth and variable fractional delay using Farrow based subfilters by means of a simple minimax optimization. This results in continuous coefficient implementation of the structure, which requires multipliers for its realization. The frequency response of such a filter across all designed bandwidths is shown in Fig. 4. It is given in two parts: first part being the magnitude response, showing stopband attenuation clearly, and second is the zoomed version of the passband region, showing the passband ripple to be 0.008 dB. The filter coefficients are thus designed and then rounded off to the nearest CSD representation using a 16-bit predesigned CSD look up table. A sample entry is shown in Table 1. This representation is a special case of signed power of two and removes multipliers from the implementation. But the rounding off of the coefficients degrades the filter response as shown in Fig. 5, giving the passband ripple to be 0.015 dB. The proposed filter is designed by optimizing the CSD rounded

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Fig. 4. Modulus of the frequency response and error of the filter with continuous coefficients.

Fig. 5. Modulus of the frequency response and error of the filter with CSD rounded coefficients.

Table 2

Performance and computational details of sub-filter fixed coefficients.

Continuous coefficient CSD rounded ABC optimization

Max. passband ripple (dB) 0.0768 0.1605 0.08459

Min. stopband attenuation (dB) -41.0352 -34.9840 -40.5988

No. of fixed multipliers 120 - -

No. of fixed adders 210 210 210

No. of adders due to SPT terms - 234 351

Total adders 210 444 561

However, it is important to reduce hardware complexity without degradation in the filter response. Thus, using optimization technique, it is ensured that all the filters with variable bandwidths and fractional delay can be reconfigured from the structure with the same performance as that using continuous coefficients, but with lower number of LUTs. By deploying optimization techniques, the performances can be improved. Here, conventional gradient-based optimization cannot be used because the search space contains integers. Meta-heuristic Algorithms are reported to be good choices

coefficients to have minimum non-zero terms as well as optimum characteristics using ABC algorithm. The frequency response for this is shown in Fig. 6, which has a passband ripple of 0.008 dB and is achieved without multipliers in the design as seen in Table 2.

The performance and computational details of the fixed subfilter coefficients of F(z, b) and G(z, d) are given in Table 2. Additionally 19 variable multipliers and 19 adders are required to implement the structure in Figs. 1 and 2.

All simulations were done using MATLAB 7.10.0 on Intel Core2 Duo CPU operating at 3 GHz.

6. Result analysis

It can be observed from Fig. 4 that the results are very similar to the results in Reference 4, where the filters are reported to result in the least complexity when compared to earlier published results. A 64% multiplications and 67% additions savings had been reported in Reference 4 when compared to the previous polynomial based realization [6].

In this paper, the coefficients are represented in the CSD space. But this is seen to degrade the performances as seen in Fig. 5. But it has only adders and shifters, and no multipliers. This would have reduced overall complexity, as suggested by their LUT utilization.

Table 3

Implementation complexity comparison of proposed method with References 4 and 6.

Design in Design in Proposed

Reference 4 Reference 6 method

Total multipliers 120 330 NIL

Total adders 210 630 561

Total LUTs 11 640 21 540 4488

0 0.2 0.4 0.6 0.8 1

x JO 3 Normalized Frequency

Normalized Frequency

Fig. 6. Modulus of the frequency response and error of the filter with ABC optimized coefficients.

16.61-1-1-.-.-.-1-.-

g. 16.2 —

O 161 _

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.42

Frequency (wt)

Fig. 7. Group delay in passband for the filter with ABC optimized coefficients.

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in such cases [9]. In this paper, the artificial bee colony algorithm is used. This makes the performances very similar to the performances in Reference 4 with continuous coefficients as seen in Fig. 6 and Table 3. There are 11 adjustable bandwidth parameters, b, evenly distributed between bl and bu. The group delay in the passband for the filter with ABC optimized coefficients is shown in Fig. 7. Since in this paper, the same number of Farrow subfilters and order of each subfilter are employed in the multiplier-less realization of the example in Reference 4, the group delay remains the same as in Reference 4. This value is reported in Reference 4 to be smaller than when the technique in Reference 6 is used. It can also be seen that d has 6 values evenly distributed between 0 and 1/2. This results in a totally multiplier-less implementation of the fixed coefficients of the FIR filters with simultaneously variable bandwidth and fractional delay. The implementation complexity of this work is compared with References 4 and 6, and is given in Table 3.

However, the total number of adders is increased by 62% when compared to Reference 4 and improved by 11% when compared to Reference 6. But multipliers are the most expensive elements in the implementation and hence this multiplier-less design will result in very low implementation complexity power dissipation, chip area and cost. By expressing the filter coefficients in SPT space, the multiplication operation is replaced by mere shifting and addition, which leads to lower power consumption and lower area during hardware implementation. The same process is followed in Reference 20 to reduce the hardware implementation complexity of the variable filter. In Reference 21, the coefficients in SPT space is further processed by means of common subexpression elimination (CSE) to reduce the number of adders. The power consumption and chip area for the entire filter structure can be explained in terms of number of the look-up-table logic (LUT) used by the hardware on a field programmable gate array (FPGA). In case of an FPGA implementation, multipliers require a large number of look up tables (LUTs). The more the number of LUTs, the more area is utilized for routing and placement of the logic. Total LUT utilization for 120 multipliers and 210 adders for the design in Reference 4 is 11 640 using Xilinx Spartan 3E. Our proposed implementation uses only 4488 LUTs, even though the number of adders have increased. The number of LUTs are provided in Table 3. Power consumption naturally decreases as area decreases. According to Reference 22, lower number of multipliers leads to lower power consumption and lower total cost. The exact factor of power reduction depends on the dynamic events of the filter input and output signals, which further depends on the application.

7. Conclusion

A method for the design and efficient implementation of Farrow-based digital filters with continuously variable bandwidth and fractional delay is presented. Fixed subfilters designed using SPT coefficients significantly reduce the overhead multipliers in the implementation. The optimal response of the filter is restored by means of ABC optimization algorithm. Thus, the sub-filters F(z, b) and G(z, d) are made totally multiplier-less, which will lead to the reduction in the implementation complexity, power dissipation and

chip area. Multipliers are costly in terms of hardware implementation area. The current design is fully devoid of multipliers. This design is reconfigurable and has low delay due to the Farrow structure based design as in Reference 4. In addition to this, having lower hardware implementation complexity (significantly lower number of LUTs) makes the design ideal for real time applications. Hence, in those applications such as systems that support different wireless communication standards and different modes, this design leads to lower complexity and added reconfigurability.

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