Scholarly article on topic 'Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics'

Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics Academic research paper on "Materials engineering"

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Microelectronic Engineering
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{"Atomic layer deposition" / "Lanthanum-oxide (La2O3)" / "Zirconium-oxide (ZrO2)" / "High-k dielectric" / "Schottky-barrier MOSFET" / Silicon-on-insulator}

Abstract of research paper on Materials engineering, author of scientific article — C. Henkel, S. Abermann, O. Bethge, G. Pozzovivo, P. Klang, et al.

Abstract Schottky barrier SOI-MOSFETs incorporating a La2O3/ZrO2 high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500°C. Excellent drive current properties, low interface trap densities of 1.9×1011 eV−1 cm−2, a low subthreshold slope of 70-80mV/decade, and an ION/IOFF current ratio greater than 2×106 are obtained.

Academic research paper on topic "Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics"

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Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics

C. Henkela'*, S. Abermanna, O. Bethgea, G. Pozzovivoa, P. Klanga, M. Stoger-Pollach b, E. Bertagnolli'

a Vienna University of Technology, Institute for Solid State Electronics, Vienna 1040, Austria

b Vienna University of Technology, University Service Center for Transmission Electron Microscopy, Vienna 1040, Austria



Article history:

Received 8 July 2010

Received in revised form 6 October 2010

Accepted 11 November 2010

Available online 17 November 2010


Atomic layer deposition Lanthanum-oxide (La2O3) Zirconium-oxide (ZrO2) High-k dielectric Schottky-barrier MOSFET Silicon-on-insulator

Schottky barrier SOI-MOSFETs incorporating a La2O3/ZrO2 high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N'-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 x 1011 eV 1 cm 2, a low subthreshold slope of 70-80 mV/decade, and an ION/IOFF

current ratio greater than 2 x 106 are obtained.

© 2010 Elsevier B.V. All rights reserved.

1. Introduction

Atomic layer deposited lanthanum-oxide (La2O3) thin films show remarkable electrical and structural properties, exhibiting a dielectric constant as high as k ~ 29, a high band gap of 5 eV, as well as a high band offset to Si as reported by Lee and coworkers

[1]. Capping these films with a second high-k oxide (e.g. ZrO2 or HfO2), the hydroxylation and related formation of La(OH)x of uncapped La2O3 films, can be circumvented. Excellent electrical properties were demonstrated by this method [2,3]. Additionally, post deposition annealing (PDA) treatments improve the dielectrics in terms of leakage current, capacitance density and interface quality

[2]. This can be attributed to the formation of a silicate interlayer between Si and La2O3, and the additional densification of the La2O3 films, which changes the permittivity of the films [2-4]. High low field electron mobilities were achieved for MOSFETs, if the silicate layer is in direct contact to Si and HfO2 is used as a capping layer [5]. Hence, capped La2O3 films are an excellent candidate for the integration into upcoming CMOS technologies.

Schottky-barrier metal-oxide semiconductor field effect transistors (SB-MOSFETs) are promising candidates to overcome problems with high external resistances from source and drain regions in next complementary metal-oxide semiconductor (CMOS) technology nodes [6], addressing the implementation of ultra thin body devices and nanowire architectures. Atomically sharp interfacial regions of the metal-silicide to the silicon (Si) channel region can

* Corresponding author. Tel.: +43 1 5880136236; fax: +43 1 5880136299. E-mail address: (C. Henkel).

0167-9317/$ - see front matter © 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.11.003

be obtained by using suitable low processing temperatures below 600 °C to form metallic source/drain regions [7]. By decreasing the effective Schottky-barrier height at the source to channel region below 0.1 eV, the drive current of a SB-MOSFET can outperform those of a conventional MOSFET as was shown by Connelly and coworkers [8]. However, only few reports exist about the implementation of high-k/metal gate technology into a fully CMOS compatible process scheme for the integration of SB-MOSFETs at low temperatures [9-11].

This paper extends the current studies on atomic layer deposition (ALD) deposited La2O3 as a gate dielectric to the integration into a low temperature process scheme for SB-MOSFET devices. A stacked La2O3/ZrO2 dielectric is applied in a high-k metal gate source/drain accumulation mode p-type SB-MOSFET. Scaled dielectric gate stacks with EOT down to 1.27 nm are presented with excellent current densities obtained for the recently developed ALD La precursor tris(N,N'-diisopropylformamidinato) lanthanum. The ALD layer of La2O3 capped with ZrO2 are promising candidates for the integration into a CMOS process flow. For the metallic source/drain regions PtSi is used. The influence of different low temperature processing schemes is investigated.

As was shown by Larrieu et al. [12] a conversion of a thin Pt layer on Si into PtSi takes place already at temperatures of 350 °C. Therefore PtSi is appropriate for the integration into low temperature processes. Moreover, PtSi is shown to yield a zero field barrier height as low as 0.14 eV to holes [13] as well as excellent current drive abilities.

Here, as the gate contact, metallic titanium nitride (TiN) is applied. This layer is capped by tungsten (W) to avoid oxidation

of the TiN film at higher annealing temperatures. TiN offers low resistivity and thermal stability in high-k dielectric capacitor structures on silicon at temperatures of up to 600 °C [14,15].

Metal-oxide semiconductor (MOS) capacitor structures on Si substrate are used to optimize the electrical properties of the deposited multilayer of La2O3 and ZrO2. The respective interface trap densities, equivalent oxide thickness (EOT), as well as the gate leakage current are evaluated.

2. Device fabrication

P-type silicon-on-insulator (SOI) wafers are used as substrates. The corresponding thicknesses of the (100) - silicon layer and the buried oxide (BOX) layer are 190 nm and 400 nm, respectively. The process flow of the formation of SB-MOSFETs is summarized in Fig. 1a.

After a standard RCA cleaning process, ALD is applied to grow the dielectric stack. The ALD reactor used is a cross-flow reactor (Cambridge Nanotech, Savannah 100). The La2O3 films are grown from the La precursor tris(N,N'-diisopropylformamidinato) lanthanum using oxygen as the oxidant agent. La2O3 films are in situ capped by ZrO2, using tetrakis-(diethylamino)-zirconium and oxygen (O2) as the precursor substances. The substrate temperature for both processes is set to 300 °C. The resulting equivalent oxide thicknesses are varied from 1.27 to 1.86 nm.

Different PDA treatments at temperatures from 350 °C to 500 °C for 5 min in argon atmosphere at a ramp rate of 10 K/s are applied. The gate contact consists of 20 nm TiN sputter-deposited by physical vapor deposition (PVD) from a sinter target. To prevent any oxidation of the TiN, it is in-situ capped by 100 nm of W.

Finally, in order to protect the gate stack against the following wet etch processing steps, it is capped with 80 nm of SiO2 deposited at temperatures of 300 °C by plasma enhanced chemical vapor deposition (PECVD), using diluted silane (2% SiH4, 98% H2), and nitrous oxide (N2O).

A Pt layer is used in the subsequent reactive ion etching (RIE) process to mask the SiO2/W/TiN stack, whereat SF6 and N2 are used as the etching gases. Afterwards, spacers with a thickness of 100 nm are formed from SiO2 by means of PECVD at 300 °C and a subsequent anisotropic RIE process with SF6/N2.

In a final step, the high-k oxide layer of La2O3/ZrO2 is selectively etched by RIE using SiCl4.

A self-aligned silicidation process is applied to form PtSi source/ drain regions, whereat the Pt layer thickness is chosen to be 60 nm. The silicidation is applied at 350 °C for 30 min in forming gas (10% H2, 90% N2) to achieve the full transformation of the Pt to platinum mono-silicide (PtSi) [12]. Finally, the unreacted Pt is etched in diluted aqua regia [14]. Fig. 1b shows a schematic of the final devices structure.

Subsequently, post metallization annealing (PMA) treatments are performed at 350 °C to 500 °C for 30 min in forming gas.

Fig. 1. (a) Process flow of the self-aligned formation of SB-MOSFETs incorporating an atomic layer deposited high-k dielectric gate stack. (b) Final structure of the processed SOI SB-MOSFET.

Metal-oxide semiconductor capacitors are fabricated by depositing La2O3/ZrO2 on a low doped n-type and RCA-cleaned Si substrate. The TiN/W gate electrode is deposited by rf-magnetron sputtering and structured by a subsequent RIE step, as given above. The electrical properties of MOS-capacitor structures are analyzed by capacitance-voltage (C-V) and current-voltage (I-V) measurements using a Keithley SCS 4200 analyzer. From the C-V measurements the equivalent oxide thickness (EOT) as well as the flatband voltage is determined. The output- and transfer characteristics are obtained from long channel p-type accumulation mode SB-MOS-FETs, whereat the gate length was varied from 1 to 40 im. Atomic layer deposited thin films are characterized by X-ray diffraction (XRD) (using a PANalytical X'Pert PRO X-ray diffraction system) and by high resolution transmission electron microscopy (HR-TEM) (using a FEI TECNAIF20 system) to investigate the morphology and the film thickness of the oxides. The physical thickness of the deposited gate dielectrics is additionally determined by using spectroscopic ellipsometry (using a Woolam, a-SE system).

3. Results

3.1. Transmission electron microscopy and X-ray diffraction measurements

On the left side of Fig. 2, a HR-TEM image taken from a processed MOSFET device shows a gate stack annealed at 350 °C. A homogeneous amorphous interfacial layer of 1.5 ±0.5 nm can be seen, whereas the bright contrast in the TEM image implies a SiOx-rich film. From the corresponding C-V measurements we obtain an EOT of 1.54 nm. Hence, it is clear that the film cannot be pure SiOx, rather it will most likely be a lanthanum-silicate-rich film formed during the PDA. A conclusion which is in agreement with results reported recently by Tsoutsou et al. [3] and Kwon et al. [16], where the formation of a silicate rich interfacial layer was observed after the annealing in nitrogen atmosphere or in vacuum. The subsequent high-k layer has a thickness of 5.2 ± 0.5 nm and reveals no sharp interface between the La2O3 and the ZrO2 phase. We conclude that the deposited film is most likely a mixed phase of La2O3/ZrO2 layer in the lower part and most pure ZrO2 in the upper part of the film. Hence, the overall physical film thickness of the dielectric stack found from HR-TEM analysis is

nm, which is confirmed by spectroscopic ellipsometry measurements. We also observe crystalline inclusions in the amorphous matrix of the oxide in HR-TEM images.

First, we evaluate the influence of different PDA treatments at 350 °C, 400 °C, and 500 °C, respectively. From XRD measurements as shown in Fig. 2b, a crystallization of the multilayered film of La2O3/ZrO2 is found at a PDA temperature of 500 °C, whereat as deposited oxide films show no indication of a crystalline phase. This is indicated by the peak in the XRD spectra at 20 = 30 degree, attributable to the higher-k tetragonal (1 0 1) or cubic (1 1 1) phase of ZrO2, which may be stabilized by the presence of La2O3, as reported in [3,17]. Small differences are found in the EOT value, which are 1.54 nm concerning the samples annealed at the lower PDA temperature and 1.45 nm concerning samples annealed at the highest PDA temperature of 500 °C. This change can be attributed to the increasing amount of the crystalline phase of the dielectric but may also be accompanied by the growth of a SiOx rich interfacial layer at the higher annealing temperatures [3,16].

3.2. Capacitance-voltage and current-voltage characteristics of La2O3/ZrO2 layers in MOS capacitors

Comparing the C-V curves shown in Fig. 3 of the ~7 nm thick La2O3/ZrO2 film to a 9 nm thick pure ZrO2 film, with comparable

Fig. 2. (a): HR-TEM image of 7 nm La2O3/ZrO2 after MOSFET device processing with both, PDA and PMA treatments performed at 350 °C. At the silicon interface a silicate rich interfacial layer with a thickness of 1.5 ± 0.5 nm is clearly distinguishable from the mixed layer of La2O3/ZrO2 featuring a thickness of 5.2 ± 0.5 nm and the amorphous topTiN-layer. The corresponding EOT amounts to 1.54 nm. (b): Comparison of XRD spectra of "as-deposited" and PDA-treated samples. The PDA is applied at 500 "C. (c): EOT as a function of the overall La2O3/ZrO2 - thickness with a corresponding PDA at 500 "C.

—a—PDA 350 *C —e— PDA 400 *C —A— PDA 500 °C —0-ZrO. 2.4-1-,-1-i-1-i-1-i-1-

Fig. 3. Capacitance-voltage characteristics for different PDA temperatures measured at f = 100 kHz of MOS capacitors with a 7 nm thick La2O3/ZrO2 dielectric stack at the same PMA treatment of 350 "C. Also the C-V characteristic of a 9 nm ZrO2 film with a similar EOT and same process parameters is shown. The upper inset shows the extracted EOT values after PMA and the lower inset shows the corresponding leakage current density.

oxide capacitance density, a shift of the flat band voltage of —-0.34V is observed if a PDA at 350 "C is applied. This shift is most likely originating from a dipole formation at the crossover of the high-k dielectric to the interface layer as reported in [18]. Also, a shift of the flatband voltage is observed to more positive voltages, if higher PDA temperatures are applied. Starting from a flatband voltage of 0.28 V for samples subjected to a PDA at 350 "C to 0.51 V for the samples subjected to a PDA at 500 "C. The change in the chemical composition of the Si/high-k interfacial layer to a SiOx-rich film upon high temperature annealing, which is also observed in [3,15], may explain the origin of this shift to more positive voltages.

Additionally, a series of La2O3/ZrO2 stacked MOS capacitors is grown with stack thicknesses of 5 nm, 7 nm and 9 nm, respectively, where at the ZrO2 capping layer thickness is varied and

the La2O3 thickness is kept constant. In Fig. 2c the EOT values of the different gate stacks are compared, whereat a PDA at 500 "C and a PMA 350 "C are applied. The EOT scales nearly linear with the physical layer thickness of the dielectric gate stack to an overall dielectric constant of k ~ 21 ± 2 obtained from the slope (dashed line, Fig. 2c) of the EOT value as a function of the physical layer thickness tOx as given in (1) [19]:

EOT - ^ tOx. (1)

Comparing three different PDA treatments of the —7 nm thick La2O3/ZrO2 film, an increase in the leakage current density, measured in the accumulation regime (at + 1 V), as shown in Fig. 4a, is found for fixed PMA temperatures of 350 "C and 400 "C. Here, an excellent leakage current density level of 15 lA/cm2 is found for the lowest PDA temperatures of 350 "C. Varying the different PMA treatments (Fig. 4b), the leakage current density is the lowest for a PMA at 350 "C, and is increasing to a value of 55 mA/cm2 for a PMA treatment at temperatures of 500 "C. This temperature dependence is most likely due to the increased crystallization of the stacked La2O3/ZrO2 layer observed, and the correlated leakage current along possible grain boundaries in the crystalline phase. The presence of crystalline inclusion may additionally affect the device performance of short channel devices, due to the variation of the dielectric constant of the oxide along the channel of the MOSFET. The variation depends on the size of crystalline inclusions and the crystalline orientations of the grains. This becomes even more important as for tetragonal ZrO2 additionally an anisotropic dielectric constant with 41.6 in the x- and y-direction is observed while a value of 14.9 is observed in the z-axis (c-direction) [20].

For the same PDA conditions at 350 "C the interface trap density plotted in Fig. 4c, as determined by the conductance technique [21] at flatband voltage conditions, decreases from the value obtained for samples without PMA treatment of 2.2 x 1012 eV"1 cm"2, to the lowest value of 1.9 x 1011 eV"1 cm"2 for samples with a PMA at 350 "C, and increases again to 3.8 x 1011 eV"1 cm"2 if a PMA at 500 "C is applied. Thus, a very low interface trap density can be obtained by keeping the thermal budget as low as 350 "C.

O 1E-4 <

■ A □ O .

□ no PMA

O PMA 350 °C

A PMA 400 °C

oG _°G ^

Fig. 4. Leakage current density obtained from MOS capacitors. In (a) different PDA treatments are performed but same PMA treatments are applied. In (b) the PDA is applied at 350 "C but different PMA treatments are performed. From (c) the interface trap density can be found comparing these respective PMA treatments.

Fig. 5. Transfer characteristics (a) of p-type SB-MOSFET devices with a 7 nm La2O3/ZrO2 gate dielectric whereat a PDA at 350 "C was applied and different PMA conditions are applied. L/W = 4/100 im. The threshold voltages are extracted at small drain voltages and are shown as a function of PDA temperature (b) as well as a function of PMA temperature (c).

3.3. SB-MOSFET devices

For different PDA and PMA treatments shown in part 2.2, the properties are now compared for a fixed gate stack thickness of 7 nm in SB-MOSFET devices processed in a fully CMOS compatible process scheme.

Fig. 5 shows the influence of different annealing treatments on the device characteristics. On the extracted threshold voltages, a pronounced influence of different PDA conditions is found as shown in Fig. 5b. The value of Uth = -0.74 V obtained for a PDA at 350 °C is shifted to a value of Uth = -0.62 V for samples with a PDA at 500 °C for fixed PMA temperature of 350 °C.

A similar shift is observed increasing the PMA temperature (Fig. 5c) and can be attributed to the change in the composition of the interfacial layer as described in part 2.2 for the change of the flatband voltage. An estimation of the variation of the SB-MOS-FET threshold voltage by the change of the Schottky-barrier height (SBH) after the PMA treatment was performed, based on the work

of Feste and coworkers [22,23]. The threshold voltage difference for SOI-SB-MOSFET devices can be estimated to be [22]:

th - dub •1 • (lndevl • t -1 - 0'06ev

Here, we take into account a shift in the Schottky-barrier height dUB of 0.02 eV concerning the different PMA annealing temperatures. This was reported for SB diode structures incorporating PtSi formed at different temperatures from 300 to 500 °C [13]. Moreover S denotes the subthreshold slope of the electron branch which was considered to be 260 mV/decade, q denotes the elementary charge, kB the Boltzmann constant and T the temperature. Hence, the shift in the observed threshold voltage is additionally caused by a variation in the SBH of the PtSi contact layer during the thermal PMA treatments. Comparing different PMA conditions, the drive current is only slightly changed, if the results are corrected for the shift in the threshold voltage. Also the subthreshold slope is nearly constant for all applied annealing conditions with

Fig. 6. Dependence of the drain current (a) on the transistor gate length for a PMA performed at 500 "C and measured Ion/Ioff current ratio (b), dependent on the PMA temperature treatment of p-type SB-MOSFET devices with a 7 nm La2O3/ZrO2 gate dielectric, whereat a PDA at 350 "C is applied. L/W = 4/100 im.

70-80 mV/decade. Concerning the n-branch leakage current of the three PMA annealing conditions the magnitude is increased about 3 orders of magnitude for the lowest PMA process at 350 "C. The main reason for this increased current is the contribution from the reverse biased drain Schottky barrier diode. However, this leakage current contribution is not influenced by the gate oxide leakage current, since for the specific gate oxide the gate oxide leakage current contribution is too low. Nevertheless, for thinner gate oxides, which exhibit higher leakage currents, the leakage current in the n-branch would be increased. Larrieu and coworkers [12] pointed out that the actual barrier height of PtSi is a function of the applied annealing condition during the formation of the PtSi silicide. Hence, concerning our source and drain the formation of PtSi may not be fully completed after the lowest PMA and silicida-tion treatment resulting in an increased reverse current density. Huang and coworkers [24] discussed comprehensively the formation of NiSi Schottky barrier diodes at temperatures of 400-800 "C. They found an increased reverse current density for NiSi diodes formed at lowest temperatures of 400 "C related to spatial barrier in-homogeneities within in the Schottky contacts. A two-phase coexistence of the metal rich Ni2Si and NiSi phase was reported for the lowest annealing temperatures of 400 "C, leading to rough interfaces at the silicon substrates. Similarly, a higher reverse leakage current is possible in our SB-MOSFET device structures, concerning the lowest PMA annealing treatments. Additionally, it was suggested that an increased drain leakage current may be caused by RIE due to induced defects at the Si interface, as reported by Kwon and coworkers [25]. Upon removal of these defects at higher annealing temperatures, the reverse current density of a formed PtSi Schottky diode structure was observed

to decrease. In our case the highest ION/IOFF current ratio can be therefore achieved by applying higher annealing temperatures to avoid the higher drain leakage currents at the lower post deposition annealing treatments.

Considering the specific performance of devices subjected to a PDA at 350 "C and a PMA at 500 "C a subthreshold swing of 71 mV/decade close to the thermal limit of 60 mV/decade is obtained at room temperature, as well as an excellent ION/IOFF current ratio greater than 2 x 106, obtained for UDS = -1 V. For the 2 im printed gate length the highest transconductance measured is 25 iS/im. The threshold voltage, obtained from a linear fit of the drain current as a function of the gate voltage for small drain to source voltages amounts to Uth = -0.43 V for the given device. The inverse subthreshold slope of the n-branch amounts to 260 mV/decade for UDS = -1.5 V. Fig. 6a shows the drive current obtained at UG = -2 V and UDS = -1.5 V as a function of the printed gate length. The linear relationship demonstrates the excellent scalability of the developed low temperature process scheme for ALD La2O3/ZrO2 gate dielectrics. Comparing the results to a PMA performed at 350 "C, whereat a smaller ION/IOFF current ratio is obtained due to the increased current contribution from the reverse current of the drain Schottky diode structure, the highest ION/IOFF ration is achieved for a PMA applied at 500 "C (Fig. 6b). However, smallest gate oxide leakage current (see Fig. 4b) was obtained from PMA temperatures lower than 500 "C. Especially for thinner gate oxide thicknesses this increase in the gate oxide leakage current would affect the ION/IOFF current ratio. Thus this trade-off may be best solved by applying a PMA at 400 "C. As shown in the output characteristics in Fig. 7, no sublinear current drive for small drain voltages is visible.

Finally, we compare the results of our low temperature process for the integration of ALD La2O3/ZrO2 to other results in the literature of SB-MOSFET devices with high-k/metal gate stacks. Zhu and coworkers [9,10] presented a simplified low temperature fabrication scheme, whereat a 5 nm HfO2 gate dielectric was deposited by MOCVD at 400 "C and subsequently annealed at 700 "C. The highest temperatures applied after the oxide deposition was 420 "C during the formation of platinum silicide. Comparing their results to the multilayered La2O3/ZrO2 dielectric processed at temperatures of 350, 400 or 500 "C a similar IOn/IOff current ratio of greater than 107 and a subthreshold slope of 66 mV/decade were obtained for p-MOSFET devices. Park and coworkers [11] studied SB-MOSFET devices with n-type channel incorporating 5 nm of ALD deposited HfO2 in a dummy gate process scheme whereat the highest temperature applied after the gate oxide deposition was 450 "C in there process flow. They find a subthreshold swing of 81 mV/decade and an ON/OFF current ratio of ~105.

We expect a further improvement of the current drive of our devices if the respective spacer thickness is decreased to optimize the overall overlap resistance, as well by decreasing the silicide to channel barrier height.

4. Discussion

The properties of a stacked La2O3/ZrO2 high-k dielectrics are investigated for the use in SOI-SB-MOSFET devices for suitable low temperature process schemes at or below temperatures of 500 °C. Electrical and structural properties of MOS capacitors are correlated to long channel SB-MOSFET devices to obtain best electrical results for atomic layer deposited La2O3, in direct contact to Si and capped by ZrO2.

Keeping the overall thermal budget as low as 350 °C, 400 °C or 500 °C a lowest interface trap density of 1.9 x 1011 eV"1 cm"2 is found. Furthermore, a high drive current is obtained for the long channel devices as well as a subthreshold swing of S = 70-80 mV/ decade. Thus, a suitable low temperature process is given for the formation of SB-MOSFETs incorporating a La2O3/ZrO2 stacked gate dielectric with low leakage current densities.

By applying suitable thermal post deposition annealing as well as post metallization annealing treatments, the threshold voltage can be effectively tuned while maintaining high drive currents. This effect is most likely induced from dipoles at the La2O3/ZrO2 to Si-interfacial layer crossover and the change in the composition of the interfacial layer upon annealing. In addition, the different PMA temperatures change the SBH and contribute to the threshold voltage shift. Also the 1ON/1OFF current ratio can be improved.

The results indicate the suitability of a La2O3/ZrO2 based material system as a potential candidate for a low temperature SB-MOS-FET based integration scheme.


This work is funded by the Austrian Science Fund (FWF), project No. P19787-N14. The Gesellschaft für Mikro- und Nanoelektronik, GMe, as well as the Zentrum für Mikro- und Nanostrukturen, ZMNS, is gratefully acknowledged for support.


[2] S. Abermann, C. Henkel, O. Bethge, C.J. Straif, H. Hutter, E. Bertagnolli, Journal of the Electrochemical Society 156 (2009) 53-57.

[3] D. Tsoutsou, L. Lamagna, S.N. Volkos, A. Molle, S. Baldovino, S. Schamm, P.E. Coulon, M. Fanciulli, Applied Physics Letters 053504 (2009).

[4] M. Copel, E. Cartier, F.M. Ross, Applied Physics Letters 78 (11) (2001).

[5] T. Kawanago, J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, Microelectronic Engineering 86 (2009) 1629-1631.

[6] International Technology Roadmap for Semiconductors,

[7] J.M. Larson, J.P. Snyder, IEEE Transactions on Electron Devices 53 (2006) 1048.

[8] D. Connelly, C. Faulkner, D.E. Grupp, IEEE Electron Device Letters 24 (6) (2003).

[9] S. Zhu, H.Y. Yu, S.J. Whang, J.H. Chen, C. Zhu, S.J. Lee, M.F. Li, D.S.H. Chan, W.J. Yoo, A. Du, C.H. Tung, J. Singh, A. Chin, D.L. Kwong, IEEE Electron Device Letters 25 (5) (2004) 268-270.

[10] S. Zhu, H.Y. Yu, J.D. Chen, S.J. Whang, J.H. Chen, C. Shen, C. Zhu, S.J. Lee, M.F. Li, D.S.H. Chan, W.J. Yoo, A. Du, C.H. Tung, J. Singh, A. Chin, D.L. Kwong, Solid-State Electronics 48 (2004) 1987-1992.

[11] B. Park, H. Lee, Y. Kim, M. Jang, C. Choi, M. Jun, T. Kim, S. Lee, Journal of the Korean Physical Society 50 (3) (2007) 893-896.

[12] G. Larrieu, E. Dubois, X. Wallart, X. Baie, J. Katcki, Journal of Applied Physics 94 (2003) 7801.

[13] E. Dubois, G. Larrieu, Journal of Applied Physics 96 (1) (2004).

[14] Ch. Wenger, M. Lukosius, I. Costina, R. Sorge, U.J. Dabrowski, H.J. Müssig, S. Pasko, Ch. Lohne, Microelectronic Engineering 85 (2008) 1762.

[15] C. Henkel, S. Abermann, O. Bethge, P. Klang, E. Bertagnolli, Impact of sputter deposited TaN and TiN metal gates on ZrO2/Ge and ZrO2/Si high-k dielectric gate stacks, in: Ultimate Integration of Silicon, 2009. ULIS 2009, 10th International Conference on ULtimate Integration of Silicon.

[16] J. Kwon, M. Dai, M.D. Halls, E. Langereis, Y.J. Chabal, Roy. G. Gordon, Journal of Physics and Chemistry 113 (2009) 654-660.

[17] P. Thangadurai, A. Bose, S. Ramasamy, Journal of Materials Science 40 (15) (2005) 3963-3968.

[18] K. Kakushima, K. Okamoto, M. Adachi, K. Tachi, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, Solid State Electronics 52 (2008) 1280-1284.

[19] G.D. Wilk, R.M. Wallace, J.M. Anthony, Journal of Applied Physics 89 (2001) 5243.

[20] X. Zhao, D. Vanderbilt, Physical Review B 65 (2002).

[21] E.H. Nicollian, J.R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, Wiley-Interscience, 1982.

[22] S.F. Feste, M. Zhang, J. Knoch, S. Mantl, Solid-State Electronics 53 (4) (2009) 418-423.

[23] R.-H. Yan, A. Ourmazd, K.F. Lee, IEEE Transactions on Electron Devices 39 (7) (1992).

[24] S. Huang, F. Lu, Applied Surface Science 252 (2006) 4027-4032.

[25] K.-H. Kwon, H.-H. Park, K.-S. Kim, C.-I. Kim, Y.-K. Sung, Journal of Applied Physics 35 (1996) 1611-1616.

[1] B. Lee, T.J. Park, A. Hande, M.J. Kim, R.M. Wallace, J. Kim, X. Liu, J.H. Yi, H. Li, M.

Rousseau, D. Shenai, J. Suydam, Microelectronic Engineering 86 (2009) 16581661.