Ain Shams Engineering Journal (2015) xxx, xxx-xxx

Ain Shams University Ain Shams Engineering Journal

www.elsevier.com/locate/asej www.sciencedirect.com

ELECTRICAL ENGINEERING

ANN based controller for three phase four leg shunt active filter for power quality improvement

J. Jayachandran *, R. Murali Sachithanandam

Department of Electrical and Electronics Engineering, SASTRA University, Thanjavur 613402, Tamil Nadu, India Received 8 November 2014; revised 9 February 2015; accepted 13 March 2015

KEYWORDS

Neural network;

DSTATCOM;

Neutral current mitigation;

Three phase four wire

distribution system;

Unbalanced and/or distorted

source;

Total harmonic distortion (THD)

Abstract In this paper, an artificial neural network (ANN) based one cycle control (OCC) strategy is proposed for the DSTATCOM shunted across the load in three phase four wire distribution system. The proposed control strategy mitigates harmonic/reactive currents, ensures balanced and sinusoidal source current from the supply mains that are nearly in phase with the supply voltage and compensates neutral current under varying source and load conditions. The proposed control strategy is superior over conventional methods as it eliminates, the sensors needed for sensing load current and coupling inductor current, in addition to the multipliers and the calculation of reference currents. ANN controllers are implemented to maintain voltage across the capacitor and as a compensator to compensate neutral current. The DSTATCOM performance is validated for all possible conditions of source and load by simulation using MATLAB software and simulation results prove the efficacy of the proposed control over conventional control strategy.

© 2015 Faculty of Engineering, Ain Shams University. Production and hosting by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction

The wide application of non-linear loads and diverse electrical loads/power sources connected to the grid increases the harmonic pollution in the utility side of ac mains. The harmonic and reactive current generated by non-linear loads/sources makes the utility side to have low power factor, decreased

* Corresponding author at: SAP, EEED, SEEE, SASTRA University, Thirumalaisamudram, Thanjavur 613402, Tamil Nadu, India. Mobile: + 91 9600441615.

E-mail addresses: jj_chandru@eee.sastra.edu (J. Jayachandran), murali@eee.sastra.edu (R. Murali Sachithanandam). Peer review under responsibility of Ain Shams University.

energy efficiency, low power handling capacity and create vulnerable disturbances to the appliances connected to the distribution system [1,2]. The conventional method like passive filter is the simplest method for harmonic reduction and power factor improvement, but suffers from drawbacks such as bulky component size, occurrence of resonance, and fixed compensation characteristics [3]. The research and development in the area of power electronics prove that active power filters are superior over the passive filters due to the evident advantages such as less response time, compact size, and better performances. In the distribution system a group of devices denoted by a generic name customer power devices (CPDs) are employed for the mitigation of the power quality problems. To solve and suppress the source voltage related problems CPD is connected in series with the load and is termed as Dynamic Voltage Restorer (DVR). The problems related to current can be solved and suppressed with the help of

http://dx.doi.org/10.1016/j.asej.2015.03.007

2090-4479 © 2015 Faculty of Engineering, Ain Shams University. Production and hosting by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

Fig. 1 Schematic power circuit diagram of 3P3W DSTATCOM and single phase inverter connected to 3P4W distribution system.

Distributed static compensator (DSTATCOM) which is a CPD connected across the load. The connection of both DSTATCOM and DVR in a grid can solve the power quality problems related to both voltage and current. This CPDs combination is termed as Unified Power Quality Conditioner (UPQC) [4-6]. In the literature survey, it is reported that for mitigation of power quality problems and for compensation of neutral current in three phase four wire (3P4W) distribution system different topologies are under investigation. They are (i) 4 leg voltage source converter (VSC) (ii) 3 single phase VSC with a capacitor (iii) 3 leg VSC with a split capacitor (iv) 3 leg VSC with any of the transformer connections such as T-connection, zig-zag, hexagonal and star-delta transformers. Most of the researchers prefer the four leg VSC topology as a better choice for the compensation of neutral current compared to other configurations, even though the control is complex and costlier [7,8]. The selection of control strategy decides the performance of power quality compensator. The factors which decide the choice of control strategy are accuracy, filter response time and number of steps involved in the calculation. In order to fulfill these requirements many control strategies are developed and proposed by various researchers. They are instantaneous reactive power theory (IRP), space vector pulse width modulation (SVPWM), power balance theory, synchronous reference frame theory (SRF) [9-11], Lyapunov-function based control [12], nonlinear control [13], etc. The above mentioned conventional control approaches calculate harmonic and reactive current components for the generation of reference currents with the help of sensors and multipliers to sense the load currents and source voltages. To perform with high speed and accuracy the controller requires high speed processor and high performance data converters for the calculation of reference current and this makes the controller to suffer from evident disadvantages such as high cost, low stability and more complexity. The control strategy for 3P active power filter (APF) first reported in the literature without reference current calculation was one cycle control (OCC) [14-18].

The conventional controllers like PI, PID, etc., perform unsatisfactorily during variation in parameters under nonlinear load conditions and require precise linear mathematical models which are hard to derive. In recent era the major effort of the researchers is to replace these conventional controllers with a new unconventional control strategy especially like neural network controller which offers best solution for many power quality problems. The neural network control algorithm can learn, remember and make decisions. The apparent advantages such as fast dynamic response, better steady state and transient stability, robustness, improved tracking and adaptive ability, accuracy and precision under parameter variation make neural network controller superior than other controllers [19]. In the control of DSTATCOM, different ANN structures have been implemented for the extraction of fundamental or harmonic load current such as adaptive neuro-fuzzy interference system (ANFIS) [20], the radial-basis-function neural network (RBFNN) [21], Adaptive Linear Neuron (ADALINE) [22], Hopfield-type [23], Anti-Hebbian [24], and Back propagation (BP) [25]. The BP and ADALINE neural network control strategies are preferably used for the control of DSTATCOM.

To accomplish the function of power quality compensator, a neural network based one cycle control algorithm for 3P4W DSTATCOM is proposed in this paper. The proposed neural network based control strategy eliminates the process of calculating the reference current and also the application of voltage sensors and multipliers, thus making the system robust and simple. The control strategy employs a neural network block, an integrator with reset, digital and linear components which drive the control variables to meet the requirement in each switching cycle with apparent advantages of high accuracy and faster response. ANN controllers are proposed to maintain voltage across the capacitor and to mitigate the neutral current under unbalanced load and source conditions. The features of proposed ANN based control strategy of DSTATCOM are (i) balanced and sinusoidal source current from the supply mains that are nearly in phase with the supply voltage, for various source and load conditions (ii) reduction

Fig. 2 Schematic diagram of proposed neural network based one cycle control.

Fig. 3 Average model of the proposed scheme to determine switching state.

in the % total harmonic distortion (THD) of source current (iii) compensation of reactive power and neutral current (iv) regulation of DC bus capacitor voltage (v) reduction in the number of sensors required when compared to conventional system (vi) elimination of reference current calculation which discards the requirement of high speed processor, data converters and multipliers (vii) reduction in switching losses due to constant switching frequency.

2. System configuration of DSTATCOM

Fig. 1 depicts the power circuit diagram of a DSTATCOM with three phase three leg IGBT based VSC and single phase inverter with a DC capacitor performing as energy buffer, connected to the 3P4W distribution network. Star connection of 3u voltage source with a neutral point realizes the 3P4W supply system. Zsa, Zsb, Zsc represent the impedance of the three phase lines and the impedance of the neutral conductor is

represented as Zsn. The coupling inductor and resistor of the DSTATCOM are represented as Lc and Rc. The capacitor Cdc maintains the DC source voltage Vdc which is feasible, since the DSTATCOM processes only powers of harmonics and reactive component. In the schematic diagram, 3P4W DSTATCOM, ripple filter and different types of loads are shunted at the point of common coupling (PCC). The DSTATCOM fired by appropriate switching signals generates compensating currents and injects into the distribution system. The mitigation of neutral current under unbalanced load conditions is accomplished by the fourth limb of DSTATCOM. The switching transients and ripples present in the PCC are filtered out by series connection of capacitor Cf and resistor Rf.

3. Proposed control strategy of DSTATCOM

The proposed control strategy is simple to be implemented in industrial applications due to its constant switching frequency

and absence of reference current calculation even when the supply voltage is distorted and/or unbalanced with unbalanced linear/non-linear loads. The switching signals for the DSTATCOM for mitigation of harmonics/reactive components are generated by a neural network block, integrator with reset, digital and linear components. A separate neural network controller is also implemented for single phase APF to mitigate neutral current under unbalanced load conditions. Two different neural network (NN) controllers are proposed in this algorithm to serve the following purposes:

(i) To extract the power loss in the inverter and interfacing inductor, thereby keep up the DC bus capacitor voltage to its reference value by compensating the power loss (NN1).

(ii) To mitigate neutral current under unbalanced load conditions through single phase APF (NN2).

The proposed neural network control strategy makes the source current and supply side voltage waveforms nearly sinusoidal under any electrical disturbances. In the proposed neural network based control strategy the control circuit for DSTATCOM is designed as two independent parts for better flexibility of operation. They are as follows:

1. ANN based control strategy for three leg VSC APF.

2. ANN based reference current generation for neutral current mitigation.

3.1. ANN based control strategy for three leg VSC APF

The three leg VSC based APF operates in four quadrant and continuous current mode (CCM), since it requires bidirectional flow of energy between the DC capacitor and source side [14-18]. Eq. (1) gives the steady state relationship between ac source voltage VS and output DC voltage Vdc.

K(d) ■ Vdc — Vs

where VS =

Vsa VA

is the ac source voltage vector and

dbn dcn

is the duty ratio vector.

K(d) is expressed as follows: K{d) — A + B ■ d where A, B are linear matrices. The main aim of the control strategy is to attain unity power factor (UPF) in all the three phases. It can be expressed as follows:

where RC is the connoted resistance that represents the active power of the load and IS is the source current vector repre-

sented as

Equating Eqs. (1) and (2) gives, Rs ■ Is — K(d) ■ Vf

where RS is the resistance of current sensor and Vf is defined as follows:

Vf — Rs ■

The signal Vf is obtained from the neural network block, which gives the information about the power loss in the inverter and interfacing inductor, thereby keep up the DC bus capacitor voltage to its reference value by compensating the power loss. In order to achieve UPF operation, the switching of the APF must satisfy Eq. (3) and it implies that APF operates on unified constant frequency integration control (UCI).

With reference to Fig. 2 the gate pulses applied to the switches in each arm are complementary. The duty ratio for lower arm switches San, Sbn, Scn is dan, dbn, dcn whereas for upper arm switches Sap, Sbp, Scp are (1 — dan), (1 — dbn), (1 — dcn). The node voltages A, B, C with respect to node N can be represented as follows:

VAN —(1 - dan) ■ Vdc; VcN = (1 - dcn )■ Vdc

VBN —(1 — dbn) ■ Vdc;

With reference to Fig. 3 node voltages for A, B, C with respect to neutral point "O" can be written as follows:

Vao — Vsa - jxL ■ iLa, Vbo — Vsb - jxL ■ iLb, Vco — Vsc - jxL ■ iLc

where iLa, iLb and iLc are inductor currents.

In Eq. (6) the impedance of inductance values of each phase is very small at line frequency thus the voltage drop across the inductor of each phase can be neglected when compared with the phase voltages. Therefore the above equation can be rewritten as follows:

For a three phase balanced source voltage

Vao + Vbo + Vco ffi vsa + va + vsc — 0

With reference to Fig. 3 the node voltages A, B, C with respect to neutral point can be represented as follows:

VS — RCIS

VAO — VAN + VNO = Vsa; VBO — VBN + VNO = Vsb;

Vco — Vcn + Vno ffi vsc

VAO = Vsa; VbO = Vsb; VcO = Vsc

Table 1 Vector operating mechanism of the proposed OCC.

Region iP In dp dn dt Qap Qan Qbp Qbn cp Qc Qn

I 0-60° ia ic dan dcn dbn Qp Qp OFF ON Qn Q„

II 60-120° -ib -ic dbp dcp dap ON OFF Qp Qp Qn Qn

III 120-180° ib ia dbn dan dcn Qn Qn Qp Qp OFF ON

IV 180-240° -ic -ia dcp dap dbp Qn Qn ON OFF Qp Qp

V 240-300° ic ib dcn dbn dan OFF ON Qn Qn Qp Qp

VI 300-360° -ia -ib dap dbp dcp Qp Qp Qn Qn ON OFF

Fig. 4 Control block of ANN based OCC for three leg VSC APF.

Fig. 5 Single phase APF control strategy.

20 1 Fig. 6 Proposed BPNN architecture for NN1.

Substitution of (9) in (8) results in 1

Vno — — 3 ■( VAN + VBN + VCN)

Substituting (10) in (9) and further simplification results as follows:

Fig. 7 Flow chart of ANN modeling.

VAN V ' sa

VBN — Vsb

VCN Vsc

Fig. 8 Performance curve of NN1.

Table 2 ANN parameters for training in MATLAB.

Parameter Values

NN1 NN2

No of training data 400 300

No of testing data 100 50

No of neurons in input layer 2 2

No of neurons in hidden layer 20 12

No of neurons in output layer 1 1

Training function LM Algorithm

(trainlm)

Performance function Mean squared error

Activation function (input/hidden/output) tansig/tansig/purelin

Maximum epochs 500 250

Learning rate 0.05 0.04

Performance goal 1e-6

Normalized range -1 to 1

Testing accuracy in % 99.4 98.93

Comparing Eqs. (5) and (11)

-2 3 1 3 1 ■ 3 dan ~Vsa~

1 3 -2 3 1 3 dbn ■ Vdc - Vsb

1 3 1 3 -2 3 . dcn V sc _

K(d) ■ Vdc - Vs

Eq. (12) has infinite solutions, as it is a singular matrix. In this paper, the solution is obtained by assuming duty ratio to be 1 or 0 for one of the switches and duty ratio for other two switches can be determined. This makes the proposed DSTATCOM to have minimum switching losses since the duty ratio of only two switches is varied for a switching frequency. For vector operation, a line cycle is equally divided into six regions as tabulated in Table 1. During 0-60° the Sbn switch is kept ON for entire period i.e., dbn — 1. Substitution of dbn value in Eq. (12) results in the following equation:

+ 2 ■ Vsg

Vdc Vdc

dbn 1 ;

2- Vsc

Vdc Vdc

Eq. (2) can be applied for the three phases a, b, c and can be rewritten as follows:

ïsa; Vsb Rc ■ ïsb;

Eq. (14) makes the DSTATCOM to operate in UPF operation. Substituting Eqs. (14) and (4) in (13) yields the following equation:

1 dan - Rs ■ "2 1" 1-sa

. 1 dcn . .1 2, . lsc .

& dbn — 1

The duty ratio dan, dcn is varied in such a way that they fulfill Eq. (15), and make the currents isa, isc to be in phase with Vsa, Vsc respectively. For a symmetrical 3 — u system, current isb will also be in phase with Vsb. Thus, during entire 0-60° region the proposed control strategy makes the 3 — u system to operate in UPF. In the next region i.e., (60-120°), the switch Sap is kept ON whereas San is OFF, thus the duty ratio value will be dan — 0, dap — 1. The control equation derived for the region (60-120°) is:

1 — dbp - Rs ■ 2 1 Isa

.1 - dcp 1 2

& dap - 1

With reference to Eqs. (15) and (16) a generalized equation can be derived for the entire region (0-360°) which is represented as follows:

2 1 1 2

& d, = 1

Vsc - Rc ■

Table 3 Comparison of performance of DSTATCOM with proposed controller and conventional OCC controller for ideal voltage source condition.

Load conditions % THD Proposed controller Conventional OCC controller Neutral current

ha iLb Ilc % THD Vdc rms (V) % THD Vdc rms (V) IsN rms (A)

Isa Isb Isc Isa Isb Isc

(i) 14.69 9.33 7.24 0.41 0.13 0.66 680 0.41 0.73 1.09 679.2 0.732

(ii) 13.07 11.73 8.92 3.17 1.39 1.49 680 3.32 2.18 1.65 679.2 0.8027

(iii) 14.15 12.70 9.17 3.28 1.10 1.38 680 3.45 2.14 1.47 679.2 0.9419

(iv) 9.68 6.09 5.46 4.47 3.42 3.73 680 3.77 2.92 3.39 679.2 0

(v) 13.33 9.11 7.23 0.28 0.14 0.24 680 0.24 0.47 0.49 679.2 0.3235

(vi) 12.81 8.26 6.85 0.45 0.62 0.71 680 0.47 0.37 0.64 679.2 0.4744

(vii) 12.90 8.15 6.86 2.93 1.31 1.98 680 2.90 1.07 1.98 679.2 0.6102

(viii) 12.86 8.35 6.82 0.38 0.48 0.49 680 0.37 0.33 0.49 679.2 0.2804

(ix) 12.78 8.45 6.81 0.36 0.41 0.43 680 0.53 0.70 0.82 679.2 0.1961

where dp, dn, dt = duty ratio of switches & ip, in = phase currents of any two phases. Using Eq. (17), various controlling parameters for the entire region (0-360°) are calculated and tabulated in Table 1. It shows that proposed neural network based OCC strategy changes its parameters for every 60°. Fig. 4 shows the control block of ANN based OCC for three leg VSC APF. The control circuit consists of three blocks:

(i) OCC core: It includes three adders, an integrator with reset, two flip-flops and comparators.

(ii) Vector operation logic: The vector operation logic performs the following functions:

(a) The selection circuit for vector region divides the line cycle into six regions in variation with zero crossing point of phase voltage Vsa.

Table 4 Comparison of performance of DSTATCOM with proposed controller and conventional OCC controller for unbalanced voltage source condition.

Load conditions % THD

Proposed controller

Conventional OCC controller

Neutral current

iLa iLb iLc % THD Vdc rms (V) % THD Vdc rms (V) Isn rms

Isa Isb Isc Isa Isb Isc

(i) 9.94 19.31 8.31 2.37 2.36 2.37 680 2.32 2.49 2.59 679.2 0.6883

(ii) 12.27 23.22 9.77 4.16 3.63 2.54 680 4.05 3.72 2.60 679.2 0.9815

(iii) 12.76 26.71 9.95 4.32 3.14 2.48 680 4.15 3.71 2.57 679.2 1.13

(iv) 9.23 11.27 6.73 4.84 4.18 3.96 680 4.47 4.00 3.78 679.2 0

(v) 9.80 17.94 8.33 2.31 2.34 2.21 680 2.28 2.41 2.31 679.2 0.3136

(vi) 9.36 15.39 7.62 2.28 2.37 2.30 680 2.29 2.36 2.31 679.2 0.4691

(vii) 9.28 15.57 8.01 3.77 3.02 2.53 680 3.75 2.98 2.59 679.2 0.6362

(viii) 9.35 15.39 7.81 2.27 2.34 2.23 680 2.27 2.35 2.26 679.2 0.2793

(ix) 9.35 15.67 7.90 2.27 2.34 2.21 680 2.85 3.12 3.40 679.2 0.1927

Table 5 Comparison of performance of DSTATCOM with proposed controller and conventional OCC controller for balanced and distorted voltage source condition.

Load conditions % THD

Proposed controller

Conventional OCC controller

Neutral current

ILa ILb ILc % THD Vdc rms (V) % THD Vdc rms (V) Isn rms

Isa Isb Isc Isa Isb Isc

(i) 12.91 8.83 6.96 2.27 2.23 2.45 680 2.47 2.54 2.72 679.2 0.4744

(ii) 13.40 12.31 8.94 4.25 2.78 3.03 680 4.82 3.69 3.20 679.2 0.8027

(iii) 14.45 13.28 9.19 4.39 2.80 3.08 680 5.09 3.83 3.21 679.2 0.9419

(iv) 9.76 6.41 5.97 4.82 3.76 4.69 680 4.25 4.01 3.86 679.2 0

(v) 12.96 8.92 6.94 2.24 2.21 2.35 680 2.40 2.45 2.45 679.2 0.2792

(vi) 12.91 8.83 6.96 2.27 2.23 2.45 680 2.31 2.29 2.41 679.2 0.4744

(vii) 12.97 8.69 6.97 3.55 2.42 3.04 680 3.59 2.47 3.03 679.2 0.6102

(viii) 12.95 8.92 6.92 2.23 2.21 2.36 680 2.28 2.28 2.35 679.2 0.2804

(ix) 12.85 9.01 6.91 2.21 2.21 2.33 680 2.72 2.95 3.14 679.2 0.1961

Table 6 Comparison of performance of DSTATCOM with proposed controller and conventional OCC controller for unbalanced and distorted voltage source condition.

Load conditions % THD

Proposed controller

Conventional OCC controller

Neutral current

ILa ILb Ilc % THD Vdc rms (V) % THD Vdc rms (V) Isn rms

Isa Isb Isc Isa Isb Isc

(i) 9.80 19.38 8.22 2.63 2.55 2.74 680 2.61 2.71 2.85 679.2 0.6882

(ii) 12.16 23.26 9.63 4.50 3.68 2.82 680 4.58 3.94 2.97 679.2 0.9815

(iii) 12.67 26.78 9.82 4.72 3.41 2.85 680 4.82 4.06 3.07 679.2 1.113

(iv) 9.21 11.27 6.77 4.94 4.02 4.29 680 4.45 4.38 3.64 679.2 0

(v) 9.67 18.03 8.23 2.55 2.50 2.52 680 2.53 2.61 2.58 679.2 0.3136

(vi) 9.22 15.49 7.53 2.45 2.52 2.60 680 2.49 2.49 2.57 679.2 0.4691

(vii) 9.15 15.66 7.92 3.84 3.12 2.76 680 3.83 3.11 2.76 679.2 0.6362

(viii) 9.21 15.49 7.71 2.43 2.48 2.49 680 2.46 2.48 2.49 679.2 0.2793

(ix) 9.20 15.78 7.81 2.44 2.48 2.46 680 2.91 3.08 3.11 679.2 0.1927

Fig. 9 Performance under ideal voltage source condition for load case (ix). Traces (i) Ideal voltage source (Vsabc) (ii) 3 — u source currents (Isabc) (iii) 3 — u load currents (ILabc) (iv) load current of linear load (IL1) (v) load current of three 1 — u bridge rectifiers with RL load (IL2) (vi) load current of three 1 — u bridge rectifiers with RC load (IL3) (vii) load current of three phase controlled bridge rectifier fired at a = 15° with RL load (IL4) (viii) source neutral current (Isn) (ix) load neutral current (ILn) (x) compensator neutral current of single phase APF (ICn) (xi) DC bus voltage of DSTATCOM (Vdc) (xii) Harmonic spectrum of load current for phase a (xiii) Harmonic spectrum of compensated source current for phase a.

Fig. 9 (continued)

(b) Selection of the vector current ip, in from the three phase source current with the help of multiplex circuit. (iii)The feedback loop includes a neural network block which extracts the power loss in the inverter and interfacing inductor, thereby keep up the DC bus capacitor voltage to its reference value by compensating the power loss and feed as input to one cycle core.

The error signal obtained by comparing Vdc and Vref is fed as input to neural network block to derive the modulating signal Vf. The OCC core incorporates the Vm signal along with ip, in vector currents in order to derive the switching drive signals Qp and Qn from the flip-flops output. The switch is ON when the Qp or Qn is 1 and OFF when it is 0.

3.2. ANN based reference current generation for neutral current mitigation

Fig. 5 depicts the block diagram of ANN based control strategy for neutral current mitigation. The 3 — u load currents are sensed and summed up using a summer. The summed up value isn is compared with reference value i*n by the ANN controller to compute the reference neutral current i*n. The output of the ANN controller is compared with a triangular wave to generate gate pulses for the single phase APF. In the proposed control strategy, ANN controller replaces the PI controller of conventional method to amplify the current error signal [26,27].

4. Design and architecture of ANN

4.1. Overview of ANN

ANN comprises of simple elements which operate in parallel. The weighted connection between the elements decides the neural network function and can be adjusted for training the neural network for a specific function. Based on the comparison of the target with the output, the network weight is altered in order to make the network output match with the target. Neural networks are trained to solve various complex functions in all research areas. In pattern mapping and function approximation problems, a multi-layer feed forward network

trained by back propagation (BP) algorithm is the most versatile and familiar network. In the training of multilayer ANN, Back propagation algorithm is considered to be the most systematic method as it adjusts the connection weights based on the information propagated back through the network.

4.2. Proposed ANN architecture

The proposed BPNN architecture for NN1 constitute an input layer, hidden layer and output layer as depicted in Fig. 6. The composition of predefined number of neurons constitutes each layer of the neural network. The input vector is fed to the input layer, and then transmitted to the consecutive hidden layer and eventually to the output layer through weighted connections. The operation of each neuron in the hidden and output layer is to take the sum of weighted inputs and to transfer the result via a non-linear activation function. The number of input vectors to the input layer is accounted by the problem and the output of the problem decides the number of neurons in the output layer. The problem specified decides the size and the number of hidden layers between the input and output layers. Initially by varying the number of neurons in the hidden layer, the optimum combination is decided based on the performance error and training period [28,29]. Fig. 7 depicts the flow chart of ANN modeling. To handle the non-linearity in the specified problem, tangent sig-moid activation function 'tansig' is the activation function implemented in the neurons of the hidden layer and a linear activation function 'purelin' is implemented in the neurons of the output layer. 'dotprod function is adopted to adjust the network weights and biases and 'adaptwb' function is adapted to tune both weights and biases. Lavenberg-Marquardt (LM) back propagation training algorithm 'trainlm' is found suitable for the specified problem, considering MSE for the L index values under varying source and load conditions, training time and overall accuracy. LM algorithm, which is the combination of Gradient Descent and Gauss-Newton methods, combines the advantages of global properties of Gradient Descent method and local conveyance properties of Gauss-Newton method. In LM algorithm the one step weight update equation is:

Aw -—(JTJ + iI) 1JTe

Fig. 10 Performance under unbalanced voltage source condition for load case (ix). Traces (i) Unbalanced voltage source (Vsabc) (ii) 3 — u source currents (Isabc) (iii) 3 — u load currents (ILabc) (iv) load current of linear load (IL1) (v) load current of three 1 — u bridge rectifiers with RL load (IL2) (vi) load current of three 1 — u bridge rectifiers with RC load (IL3) (vii) load current of three phase controlled bridge rectifier fired at a = 15° with RL load (IL4) (viii) source neutral current (Isn) (ix) load neutral current (ILn) (x) compensator neutral current of single phase APF (ICn) (xi) DC bus voltage of DSTATCOM (Vdc) (xii) Harmonic spectrum of load current for phase b (xiii) Harmonic spectrum of compensated source current for phase b.

Fig. 10 (continued)

where J represents the Jacobian matrix of the first order partial derivatives, I and i represent the identity matrix and control parameter respectively and e is the error vector. It is inferred from Fig. 8 that error decreases as the number of epoch increases and converges after 500 epochs to reach the goal. The details of ANN architecture of the proposed two neural network controllers are (NN1 and NN2) listed in Table 2.

5. Simulation results and discussions

The validation of performance of the proposed neural network control is adjudged using MATLAB/Simulink software. Appendix A lists out the details of system parameters. The performance of the propounded scheme for THD reduction, balancing of load, reactive power compensation and mitigation of neutral current is analyzed for varying load and source conditions. The simulations are also carried out using conventional

OCC controller for all the varying source and load conditions. The performance of the DSTATCOM with conventional OCC controller is compared with that of neural network control strategy in Tables 3-6. The performance of the propounded DSTATCOM with ANN control strategy is analyzed for the following load conditions.

(i) Linear unbalanced load.

(ii) Non-linear load [Three 1 — u bridge rectifiers with RL load (i.e., R and L are in series)].

(iii) Non-linear load [Three 1 — u bridge rectifiers with RC load (i.e., R and C are in parallel)].

(iv) Non-linear load [3 — u controlled bridge rectifier fired at a = 15° with RL load].

(v) Non-linear load [Three 1 — u bridge rectifiers with RC load] + Linear unbalanced load.

(vi) Non-linear load [3 — u controlled bridge rectifier fired at a — 15° with RL load] + Linear unbalanced load.

Fig. 11 Performance under balanced and distorted voltage source condition for load case (ix). Traces (i) balanced and distorted voltage source (Vsabc) (ii) 3 — u source currents (Isabc) (iii) 3 — u load currents (ILabc) (iv) load current of linear load (IL1) (v) load current of three 1 — u bridge rectifiers with RL load (IL2) (vi) load current of three 1 — u bridge rectifiers with RC load (IL3) (vii) load current of three phase controlled bridge rectifier fired at a = 15° with RL load (IL4) (viii) source neutral current (Isn) (ix) load neutral current (ILn) (x) compensator neutral current of single phase APF (ICn) (xi) DC bus voltage of DSTATCOM (Vdc) (xii) Harmonic spectrum of load current for phase a (xiii) Harmonic spectrum of compensated source current for phase a.

Fig. 11 (continued)

(vii) Non-linear load [Three 1 — u bridge rectifiers with RC load] + Non-linear load [3 — u controlled bridge rectifier fired at a = 15° with RL load].

(viii) Linear unbalanced load + Non-linear load [Three 1 — u bridge rectifiers with RL load ] + Non-linear load [3 — u controlled bridge rectifier fired at a = 15° with RL load].

(ix) Linear unbalanced load + Non-linear load [Three 1 — u bridge rectifiers with RL load] + Non-linear load [Three 1 — u bridge rectifiers with RC load] + Non-linear load [3 — u controlled bridge rectifier fired at a = 15° with RL load].

The DSTATCOM with neural network control strategy is simulated for the above nine varying load conditions with the following four different utility conditions of source voltage:

Case A: Ideal voltage source condition.

Case B: Unbalanced sinusoidal voltage source condition.

[Magnitude unbalance of 15% sag in phase a, b, c and

phase unbalance of 20°, —120°, 120°.]

Case C: Balanced [no unbalance in magnitude and phase]

and distorted voltage source condition [i.e., 15% of 3rd

and 5th harmonic are injected into the source].

Case D: Unbalanced [Magnitude unbalance of 10% sag in

phase a, b, c and Phase unbalance of 20°, —120°, 120°]

and distorted voltage source condition [i.e., 15% of 3rd

and 5th harmonic are injected into the source].

The Performance of the DSTATCOM with neural network control strategy is analyzed and tabulated for all the nine types of loads with the four cases of voltage source condition in Tables 3-6. Due to limitation in the number of pages, the waveforms are shown only for case (ix) of load condition with all the four cases of voltage source conditions.

Case ix: Linear unbalanced load + Non-linear load [Three 1 — u bridge rectifiers with RL load] + Non-linear load [Three

1 — u bridge rectifiers with RC load] + Non-linear load [3 — u controlled bridge rectifier fired at a = 15° with RL load].

5.1. Case A: Performance of DSTATCOM under ideal voltage source condition

To study the effect of ideal voltage source condition in DSTATCOM, a three phase voltage source of 415 V, 50 Hz, with phase difference of (0°, —120°, + 120°) is applied for the entire period. The DSTATCOM dynamic performance for the above mentioned source condition is depicted in Fig. 9. Source currents are balanced and sinusoidal after the compensation of harmonic currents. It is also observed that the dc bus voltage is maintained at its reference value. The propounded neural network control algorithm reduces the THD of the compensated source current to 0.36%, 0.41%, 0.43% for phases a, b, c whereas the load current THD is 12.78%, 8.45%, 6.81% respectively. The THD of the compensated supply current is within 5% which is the benchmark value of IEEE-519 recommendation. DSTATCOM with conventional control strategy reduces the %THD of the source currents to 0.53%, 0.70%, 0.82% for phases a, b, c as depicted in Table 3. From Fig. 13(a)-(c) it is evident that the performance of the DSTATCOM with proposed control strategy is superior than conventional control strategy in reducing the % THD of the source current. The neural network based single phase APF reduces the source neutral current from 9.36 A to 0.1961 A which is nearly zero. The compensation neutral current Icn is in phase opposition with the uncompensated neutral current ILn, which verifies proper neutral current compensation.

5.2. Case B: Performance under unbalanced sinusoidal voltage source condition. [Magnitude unbalance of 15% sag in phases a, b, c and phase unbalance of 20°, —120°, 120°]

In many practical applications, the possibility of occurrence of unbalanced source voltage is more, which may cause a zero-

Fig. 12 Performance under unbalanced and distorted voltage source condition for load case (ix). Traces (i) unbalanced and distorted voltage source (Vsabc) (ii) 3 — u source currents (Isabc) (iii) 3 — u load currents (ILabc) (iv) load current of linear load (IL1) (v) load current of three 1 — u bridge rectifiers with RL load (IL2) (vi) load current of three 1 — u bridge rectifiers with RC load (IL3) (vii) load current of three phase controlled bridge rectifier fired at a = 15° with RL load (IL4) (viii) source neutral current (Isn) (ix) load neutral current (ILn) (x) compensator neutral current of single phase APF (ICn) (xi) DC bus voltage of DSTATCOM (Vdc) (xii) Harmonic spectrum of load current for phase b (xiii) Harmonic spectrum of compensated source current for phase b.

Frequency (Hi)

Fig. 12 (continued)

sequence voltage in the distribution system. To study the effect of unbalance in DSTATCOM a magnitude unbalance of 15% sag is made to occur in phases a, b, c for the time period between t = 0.25 s and 0.35 s and phase unbalance of 20°, — 120°, 120° for the entire time period. The DSTATCOM dynamic performance for the above mentioned source condition is shown in Fig. 10. Source currents are balanced and sinusoidal after the compensation of harmonic current. It is also observed that the dc bus voltage is maintained at its reference value. The propounded neural network control algorithm reduces the THD of the compensated source current to 2.27%, 2.34%, 2.21% for phases a, b, c whereas the load current THD is 9.35%, 15.67%, 7.90% respectively. The THD of the compensated supply current is within 5% which is the benchmark value of IEEE-519 recommendation. DSTATCOM with conventional control strategy reduces the %THD of the source currents to 2.85%, 3.12%, 3.4% for phases a, b, c as depicted in Table 4. From Fig. 13(d)-(f) it is evident that the performance of the DSTATCOM with proposed control strategy is superior to conventional control strategy in reducing the % THD of the source current. The neural network based single phase APF reduces the source neutral current from 9.52 A to 0.1927 A which is nearly zero. The compensation neutral current Icn is in phase opposition with the uncompensated neutral current ILn, which verifies proper neutral current compensation.

5.3. Case C: Performance under balanced [no unbalance in magnitude and phase] and distorted voltage source condition [i.e., 15% of 3rd and 5th harmonic are injected into the source]

The frequency of occurrence of distorted source voltage condition is likely to be more in many practical applications, which may cause a zero-sequence voltage in the distribution system. To study the impact of distorted source voltage condition in DSTATCOM, 15% of 3rd and 5th harmonic are injected into

the source for a time period of 0.35s to 0.5s. The DSTATCOM dynamic performance for the above mentioned source condition is shown in Fig.11. Source currents are balanced and sinusoidal after compensation of harmonic currents. It is also observed that the dc bus voltage is maintained at its reference value. The propounded neural network control algorithm reduces the THD of the compensated source current to 2.21%, 2.21%, 2.33% for phases a, b, c whereas the load current THD is 12.85%, 9.01%, 6.91% respectively. The THD of the compensated supply current is within 5% which is the benchmark value of IEEE-519 recommendation. DSTATCOM with conventional control strategy reduces the %THD of the source currents to 2.72%, 2.95%, 3.14% for phases a, b, c as depicted in Table 5. From Fig. 13(g)—(i) it is evident that the performance of the DSTATCOM with proposed control strategy is superior to conventional control strategy in reducing the % THD of the source current. The neural network based single phase APF reduces the source neutral current from 9.45 A to 0.1961 A which is nearly zero. The compensation neutral current Icn is in phase opposition with the uncompensated neutral current ILn, which verifies proper neutral current compensation.

5.4. Case D: Performance under unbalanced sinusoidal voltage source condition. [Magnitude unbalance of 10% sag in phases a, b, c and phase unbalance of 20°, —120°, 120°] and distorted voltage source condition [i.e., 15% of 3rd and 5th harmonic are injected into the source]

When the source voltage is distorted and also unbalanced, the magnitude of zero sequence voltage is very high and the impact on the load is also critical. To study the impact of distorted and unbalanced voltage source condition in DSTATCOM, a magnitude unbalance of 10% sag is made to occur in phases a, b, c for the time period between t = 0.25 s to 0.35 s and phase unbalance of 20°, —120°, 120° for the entire time period along

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Fig. 13 Comparison of % THD of source currents with proposed and conventional controller for nine load conditions. (a-c) Ideal voltage source condition. (d-f) Unbalanced voltage source condition. (g-i) Balanced and distorted voltage source condition. (j-l) Unbalanced & distorted voltage source condition.

with 15% of 3rd and 5th harmonic is injected into the source for a time period of 0.35 s to 0.5 s. The DSTATCOM dynamic performance for the above mentioned source condition is shown in Fig. 12. Source currents are balanced and sinusoidal after compensation of harmonic current. It is also observed that the dc bus voltage is maintained at its reference value. The propounded neural network control algorithm reduces the THD of the compensated source current to 2.44%, 2.48%, 2.46% for phases a, b, c whereas the load current THD is 9.20%, 15.78%, 7.81% respectively. The THD of the compensated

supply current is within 5% which is the benchmark value of IEEE-519 recommendation. DSTATCOM with conventional control strategy reduces the %THD of the source currents to 2.91%, 3.08%, 3.11% for phases a, b, c as depicted in Table 6. From Fig. 13(j)-(l) it is evident that the performance of the DSTATCOM with proposed control strategy is superior to conventional control strategy in reducing the % THD of the source current. The neural network based single phase APF reduces the source neutral current from 9.78 A to 0.1927 A which is nearly zero. The compensation neutral current Icn is

in phase opposition with the uncompensated neutral current ILn, which verifies proper neutral current compensation.

The dynamic performance of the neural network based proposed system is validated using the following inferences made from the simulation results.

(i) Under all changing conditions of load and source, the source currents are sinusoidal, balanced and nearly in phase with supply voltage. The % THD of the compensated source current is well below 5% which is bench mark value of IEEE-519 standard, whereas the % THD of the uncom-pensated source current is high.

(ii) When the 1 — u APF is switched ON, the neutral current of the source is nearly zero and this ensures proper neutral current compensation.

(iii) It is also inferred from the waveform that the DC bus voltage of the DSTATCOM is retained at the reference value under all varying load and source conditions.

(iv) Compensated source current THD is well below 5% even for unbalanced and distorted source voltage condition which makes the load more critical. Harmonic mitigation is achieved effectively in spite of high harmonic content of supply voltage.

(v) Based on the performance comparison of DSTATCOM with proposed controller and conventional OCC controller for varying source and load conditions in Tables 3-6. It is inferred that

• The % THD of the source currents with proposed and conventional controller under different voltage source conditions compared in Fig. 13(a)-(l) clearly depicts that the performance of the proposed neural network controller is better than that of conventional controller.

• Single phase APF with proposed neural network controller mitigates source neutral current nearly to zero.

• The voltage across the DC bus capacitor is well regulated at 680 V using proposed controller compared to the conventional OCC controller.

6. Conclusion

A neural network based control strategy is proposed and has been implemented for the DSTATCOM in 3P4W distribution system. The proposed control strategy performance is evaluated for all possible source conditions with varying nine types of non-linear and linear loads. The propounded DSTATCOM performance has been investigated and validated through simulation employing MATLAB/Simulink software. The simulation results and tabulation prove the efficacy of the control strategy over conventional OCC control under varying load and source conditions. The dynamic performance of the neural network based D-STATCOM is validated and highlighted using the following inference made from the simulation results.

(i) Compensation of harmonic content.

(ii) Under all changing conditions of load and source, the supply currents are sinusoidal, balanced and nearly in phase with supply voltage.

(iii) Reactive power compensation.

(iv) Compensation of neutral current under unbalanced linear and non-linear loads.

(v) Maintenance of DC capacitor voltage to its reference value under all operating conditions.In addition, the proposed control scheme reduces the source current's THD well below 5% which is the bench mark value of IEEE-519 standard.

(vi) The performance of the DSTATCOM with proposed controller is found to be superior to conventional OCC controller for all varying source and load conditions.

Appendix A. Simulation parameter.

Parameter Value

Rated source voltage Three phase four wire system, 415 V,

Impedance of the line Rs = 0.02X, Ls = 1.6 mH.

DC bus voltage of 680 V

D-STATCOM

DC bus capacitance of 3000 iF

D-STATCOM

D-STATCOM Rc = 1X, Lc = 2.5 mH

coupling inductor

Single-phase APF Rc = 1X, Lc = 0.5 mH

coupling inductor

Ripple filter Rf = 5X, Cf = 5 iF

(i) Linear Phase-a 25.93 kVA, Phase-b 50.47 kVA,

Phase-c 75.31 kVA

(ii) Non-Linear load Case (a) Three single-phase bridge

rectifier with RL load connected between

the phase-a and neutral with

load Rdc = 2X, Ldc = 1 mH

the phase-b and neutral with

load Rdc = 3X, Ldc = 2 mH

the phase-c and neutral with

load Rdc = 6X, Ldc = 1 mH

Case (b) Three single-phase bridge

rectifier with RC load connected between

the phase-a and neutral with

load Rdc = 2X, Cdc = 9 iF

the phase-b and neutral with

load Rdc = 3X, Cdc = 5 iF

the phase-c and neutral with

load Rdc = 7X, Cdc = 10 iF

Case (c) Three phase controlled bridge

rectifier fired at a = 15° with RL load

where Rdc = 2X, Ldc = 4 mH

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J. Jayachandran was born in India. He received the B.E. degree in Electrical and Electronics Engineering from Kongu Engineering College, Tamilnadu in 1999 and M.E. degree in Power Electronics and drives from SASTRA University, Thanjavur Tamilnadu in 2000. Presently Pursuing Ph.D. in the area of Power quality and Power electronics. He has been Senior Assistant Professor in School of Electrical and Electronics Engineering. SASTRA University, Thanjavur, Tamilnadu, India. His areas of interest are Power Quality and Power Electronics.

Dr. R. Muralisachithanandam, has received B.E degree in Electrical and Electronics from PSG college of Technology, Coimbatore in the year 1986 and M.Tech in Power Systems from Annamalai University Chidambaram in the year 1990 and obtained his doctoral degree in SASTRA University. His areas of interest are Power Quality and Power Electronics.