Force-Balance Interface Circuit Based on Floating MOSFET Capacitors for Micro-Machined Capacitive

Accelerometers

José María Gómez, Member, IEEE, Sebastián A. Bota, Member, IEEE, Santiago Marco, Member, IEEE, and

Josep Samitier, Member, IEEE

Abstract—The feasibility of a force-balance interface based on a second-order delta-sigma (AS) modulator for capacitive sensors has been analyzed in order to delimit the requirements to assure system stability for a given set of constraints related to the sensormodulator system. A AS modulator based on a switched-capac-itor architecture with floating MOSFET capacitors has been implemented using a 0.7-/xm CMOS process. Nonlinear effects related to voltage dependence of the floating MOSFET capacitors have been avoided using a modulator architecture based on charge integrators. The behavior of the new proposed modulator has been measured experimentally and compared with an equivalent interface made with lineal capacitors. Similar results were obtained from both systems. In both circuits, the modulator resolution was better than 14 bits at a sample frequency of 250 kHz, and oversampling ratio of 256.

Index Terms—Accelerometers, delta-sigma (AS) modulators, force-balance (FB) interfaces, MOSFET capacitors, switched-ca-pacitor (SC) circuits.

I. Introduction

HIGH-performance accelerometers are increasingly needed in automobile air-bag systems, navigation, seismometry, and space applications. Many transduction techniques and several devices with tens of micro-g resolution have been reported [1], [2]. Considerations such as cost, yield, performance, and power consumption [3] are powerful incentives for integrating these devices together with analog and mixed-signal circuits, such as data conversion, on the same chip [4] or in two-chip implementations [5].

Oversampling techniques based on AS modulation have been widely applied to implement the interfaces between analog and digital signals in VLSI systems [6]. This approach is relatively insensitive to imperfections in circuit components and offers numerous advantages for the realization of high-resolution analog-to-digital converters (ADCs) in comparison with Nyquist-rate converters. There are a number of architectures that can be used for the modulator, but probably, the most robust way of implementing a delta-sigma (AS) converter is by using switched-capacitor (SC) techniques. A signal-to-noise

Manuscript received June 16, 2003. This paper was recommended by Associate Editor S. Baglio.

J. M. Gómez, S. Marco, and J. Samitier, are with the Sistemes d'Instru-mentació and Comunicacions Research Group, Departament d'Electrónica, Universitat de Barcelona, 08028 Barcelona, Spain (e-mail: jm.Gomez@ub.edu).

S. A. Bota is with the Grup de Tecnología Electrónica, Universitat de les Illes Balears, 07122 Palma, Spain (e-mail: sebastia.bota@uib.es).

Digital Object Identifier 10.1109/TCSII.2006.875315

distortion ratio (SNDR) of 94 dB over 250-kHz bandwidth has been reported for a monolithic AS modulator implemented using SC circuits [7].

The objective of this work has been to demonstrate the possibility of implementation of a second-order AS modulator that can deliver an adequate dynamic range suitable for its application in capacitive sensor interfaces, using low-cost CMOS technology, and, try to solve two of the main drawbacks that arise from this task: ensure system stability for closed-loop operation, and optimize the large additional area used for the various capacitors in the SC interface.

The paper is organized as follows, after the introduction presented in Section II, we provide background on the capacitive accelerometer model and characteristics, and present the most popular measurement techniques for micro-machined capacitive sensors. Afterwards, in Section III, some aspects related with the design of a force-balance (FB) interface design are discussed, with special emphasis on the analysis of system stability. In Section IV, we present a AS modulator SC architecture based on floating MOSFET capacitors. Experimental results are presented in Section V, the proposal has been validated by comparing the characteristics of the proposed interface with an equivalent circuit made with lineal capacitors. Finally, conclusions are presented in Section VI.

II. Capacitive Accelerometer Characteristics

In recent years, there is a wide proliferation of capacitive-type sensors in accelerometer applications [8]. The reasons are that capacitive sensors are intrinsically insensitive to temperature, present high sensitivity and resolution, low power consumption and low drift.

A. Accelerometer Capacitive Model

Fig. 1(a) shows the plan view of an accelerometer based on an inertial mass. The inertial mass is used as a reference electrode (E2), which is between the other two (E\ and E3), with the whole system acting as a differential capacitor. When acceleration is applied to the sensor, the mass is displaced, and the distance between the electrodes is modified [Fig. 1(b)]. The capacitance between the terminals E\ and Ei (C12), and terminals E2 and Es (C23) can be expressed as

eA d eA

1057-7130/$20.00 © 2006 IEEE

eA ^^sAx d2 \\-:f.)'r~'~7¡'

x(s) a{s)

There are three basic measurement techniques for differential capacitive sensors that can be implemented using SC architectures [10]. These are:

• charge amplification (CA);

• charge balance (CB);

• FB."

In CA, a reference voltage ( V'rof ) is applied to both capacitors (C12 and C23). This voltage introduces an electric charge whose difference is converted into a voltage, using a reference capacitor (Crcf). We obtain a voltage output signal proportional to AC and Vrcf

Fig. 1. Accelerometer diagram: (a) in steady state, and (b) under an acceleration in the x-axis direction.

where (s) is the dielectric permittivity (air in this case), d is the sensing gap distance, A the electrode area, and x is the displacement produced by the acceleration. Measurement of the difference between the capacitors (AC) makes it possible to obtain the displacement value

y _ Ci2J^C23

The main drawback of this technique is that it introduces electrostatic forces. Because these forces are proportional to AV2/d2, while the capacitance is proportional to A/d, the CA solution is especially adequate for macroscopic sensors, where the distance between electrodes is relatively high.

The CB method tries to balance the electrostatic forces in both capacitors. This leads to a linear interface in capacitive sensors with parallel electrodes, where according to [11]

The displacement is linearly related to the acceleration (a) through the seismic mass (m) and the accelerometer spring constant (K)

C12 + C23

Hence, we can relate a with a difference between capacitances as

By detecting the capacitance changes, we can measure the acceleration. This approximation is valid for small displacements . The dynamic characteristic of the sensor can be modeled by [9]

If the sensor electrodes are not always parallel (as in rotating sensors), we will find intrinsically nonlinear behaviors. In this case the best solution is the FB method, where the proof mass is attained by enclosing the proof mass in a negative feedback loop. The feedback loop measures deviations of the proof mass from its nominal position produced by the acceleration and applies an electrostatic force to keep the proof mass centered. The accelerometer output is taken as the force needed to maintain the position. By maintaining small deflections, nonlinearities are minimized. Because the output is dependent only on the feedback force, the device is first-order insensitive to variations in the mechanical spring constant and V oc a.

We will focus on the last method because it offers the potential of wide dynamic range [1] and is applicable for any sensor geometry [9], although stability aspects must be taken into account during the interface design.

where oj0 is the accelerometer resonant frequency, oj0 — yjK/m,mthe accelerometer seismic mass, and £ the damping factor. Notice the second-order characteristic of (5).

B. Capacitance Transduction

With recent micromachining technology, this type of sensor can be fabricated with a reduced size. However, the necessary detection of small variation of the capacitance is challenging. Typical sensor capacitance is 100 fF, its variation is only «0.1 fF, and it may have to be detected with a resolution of the order of 1 aF [5].

III. Functional Design

There are two basic alternatives for introducing a differential capacitive sensor inside a AS modulator. The first one is to adapt the input stage of the AS modulator, but maintaining the modulator outside the measurement loop. The second possibility is to include the modulator inside the loop and take advantage of intrinsic benefits of feedback [12]. The possible disadvantages of this second solution are the difficulty of implementing differential-mode architectures [13] and assure system stability.

(z) = — = Kg^ {Z> ~ a ~ 1 +

where B is the accelerometer viscous term and (Vref) a voltage source that generates the electrostatic force. The resulting values for our specific accelerometer are Ca — 834 fF, K$ — 0.448, cjo = 2.0 • 104 rad/s and £ = 1.5 [11]. The next step is the determination of the £-plane transfer function of the accelerometer applying the unity pulse invariance method to (5)

BlZ + B0

Fig. 2. Transfer function of the sensor-interface system.

A. Modulator Architecture

Choosing the implementation technique and modulator architecture are the first steps of the modulator design process. In this design, the SC technique has been used in the implementation of the proposed modulator. A second-order AD modulator has been preferred, in order to maximize the ratio between processing efficiency and design effort.

B. Stability Analysis

The accelerometer acts as a second-order filter. The second-order characteristic of (5) with the second-order modulator gives a fourth-order system that can be driven in an unstable condition in a variety of situations (i.e., start up, power-supply bouncing, unbound input signals). In order to design the modulator for a proper functioning, the stable region of operation must be known [14]. The system transfer function can be obtained from inspection of the block diagram presented in Fig. 2

z2 -hA^ + Ao

' fs senh

hs—e fs coshi v- ] + —e fs senh

\fsj U

where fs is the sampling frequency and uo and a, respectively,

when M(z) and F^(z) are substituted into (8), the result is an expression related to a fourth-order system. Assuming that the acceleration bandwidth is lower than fs and our accelerometer has a damping factor close to 1, we obtain

C„K„ BlZ + B0

~ Cref z4 + A3z3 + A2z2 + AlZ + A0 1

A3 =--2Po - 2e"7T

where Ca — 2eoA/d, Kg, and K$ are the position dependency on the acceleration and the AE output, M(z) is the accelerometer z-plane transfer function, and Fas (z) is the AE modulator one.

can be obtained from the (5) applying the unity pulse invariance method [15]. The transfer function of a second-order AE modulator can be written as [7]

where (go) is the integrator gain, which in SC architectures depends on the capacitors matching. Its ideal value is 1/2. (P0) is the fraction of the output voltage that is integrated with the input value. The ideal value is 1, but this is usually lower due to the finite gain of operational amplifiers used to build the integrators

A0=RB0+ (Po B1= 1 B0 =e

where R is a feedback factor defined as

e fs + —e fs

Po = l

K — I ¿At/2 I ^ — 2 Kd3 ref -, _o£0A V2

1 Z K-W.3 ref

2 Vmf K

CgKs Cref

The values of Ca, Ks, ooo, and £ can be computed from the accelerometer parameters as [16]

A dependence between uq and the maximum allowed feedback factor can be extracted from (14). To do this, we have substituted z by e%e, and searched the solutions that have all the poles of the transfer function inside the unity circle. This happens when the feedback factor is lower than a given threshold value labeled as i?max (Fig- 3).

The modulator sampling frequency divided by the oversam-pling ratio must be greater than the sensor bandwidth. Because

where k is the Boltzman constant, T is temperature, and (AV) the desired voltage resolution. For a modulator resolution of 16 bits working with a reference voltage ofVr = 2.5 V Ay is given by

100 10000 Frequency [Hz]

Fig. 4. System resolution versus feedback factor (#).

Fig. 3. Feedback factor (r) versus oversampling cj0//s .

and sensor bandwidth are related, is possible to calculate the minimum sampling frequency for a given oversampling ratio.

C. Modulator Parameters

Readout resolution depends on the noise performance of the interface chip, which is mainly determined by front-end charge integrator kT/C noise, input amplifier 1// noise, and switching noise. The dominant thermal noise sources are usually the sampling capacitors of the first stage; thus, the reference capacitor must satisfy

Fig. 5. FB interface schematics. Two phases S1 and S2 with different time amplitude have been generated.

Then Cref > 1.4 pF. A feedback factor of 0.23 has been calculated using (15) for a reference capacitor of 1.6 pF. This value is smaller than 1, so it does not affect system stability, as is shown in Fig. 3. and the use of a compensator circuit as described in [17] is not necessary.

The modulator Nyquist frequency is another key parameter. Taking into account the sensor bandwidth, we define it as 2 kHz. This supposes that for a resolution of 16 bits, the sampling frequency must be greater than 1 MHz [7], then coo/fs — 2-3, which features a i?max «100. Fig. 4 shows the effect of R on the system resolution. Note that the feedback factor related with our accelerometer is very small compared with i?max, therefore the system resolution is similar to the one that we have with a second-order modulator.

IV. Circuit Design

The circuit that has been developed is based on a two-phase implementation. This makes possible to measure the difference between the two capacitances of the sensor. The analog part of the modulator is shown in Fig. 5. We also have a digital-to-force

Fig. 6. SC integrator schematics.

modulator based on the different duration of the phases S1 and S2. The output signal (6) is used to establish this phase duration. When S is high, the first phase (SI) is three times longer than the second one (S2), while when 6 is low, S2 is three times SI. This difference between phase lengths produces an electrostatic force that balances the input force, resulting in the FB implementation. Both synchronizing signals have been generated by an on-chip digital state machine.

The signals R1 and R2 depend on the output values SI and S2. They are used to obtain a positive or negative reference charge, depending on S.

In this context, some features of the blocks are very important and must be optimized. Particular attention was devoted to the design of the operational amplifier, which is the most demanding cell of the architecture. Another key point that requires particular attention is how capacitors are integrated. These devices can occupy a considerable area, and therefore selection of an area-efficient capacitor becomes highly desirable.

Fig. 7. AS modulator based on floating-gate capacitors. The charge integrator is shown inside the dashed box.

A. Gate Capacitors

If area has a considerable importance in the total circuit cost function, the native MOSFET capacitors (or gate capacitors), widely available in any digital process, seem to be a promising alternative to avoid the use of more expensive processes. They present higher values than double poly capacitors and good matching properties. Relative mismatching as low as 0.02% has been reported [18]. For this option, it is necessary to assure that it is possible to compensate for or correct their strong voltage dependence in order to minimize their affect on the performance of the modulator [19].

Instead of choosing a single MOSFET gate as a basic capacitive structure, we have used a couple of floating gate capacitors connected in antiparallel. In this structure the capacitance of both gates is enhanced in such a way that dependence on voltage is reduced.

B. Switch Capacitor Circuits Using Gate Capacitors

The use of MOS capacitors inside a SC circuit has been previously considered as an alternative to metal or double poly capacitors, and high-performance A£ implementations based on MOS capacitors have been reported [20]. Most of these reported solutions are based on fixing the operation point of MOS capacitors in their accumulation region, where the capacitor presents its maximum capacitance and minimum voltage dependence. A different approach is proposed in this work. The behavior of the MOS capacitor can be expressed as

where A is the capacitors area, Co is a scale factor related to technological parameters and is independent of the voltage between the capacitor terminals (V), and fv(V) is a nonlinear function that collects all voltage dependences. In linear capacitors Co is the capacitance per unit area and fv(V) — 1- Therefore, the charge-voltage relation is given by

where Q is the charge stored in the capacitor.

Using the charge conservation law, we obtain the integrator discrete-time equations for the SC integrator (Fig. 6)

QoN = Qo[n-l] + Qi[n- 1] v ГгЛ _QoM_

Уо[Щ - A0Cofv(V0[n])'

Although the charge integration process is linear, the integrator output, V0[n], is accumulating the nonlinearities of the input capacitor (C^), introducing harmonic distortion.

A different result will be obtained from the analysis of the charge integrator presented in the schematics of Fig. 7. In this case, we consider that the input and the output signals are charges instead of voltages. The charge integrator is described by the following discrete-time difference equations:

Qm[n] = Qm[n ~ 1] + Qi[îl ~ 1]

VmM = AmC^fv(ym[n}) Q0[n] = AoC0fv (Уш[п]) Vm[n].

These equations can be rewritten as

f Q0[n] = AoC0fv (Vm[n]) AmC?^m[w]) I Qm[n] = Qm[n ~ 1] + Qi[n ~ 1]

The expression (22) can be simplified, obtaining a set of difference equations that only depend on area ratios between capacitors

Qo[n] = (Qm[n - 1] + Qi[n - 1

Qo[n] =-r^-Qiln - 1] + Qo[n - 1].

The resulting charge integration process is linear assuming that we use gate capacitors that have the same voltage dependence and Co (as occurs with the MOS gates inside a VLSI die). In our particular application, the accelerometer gives a charge input Qi [n]; thus we can take advantage of linear properties of charge integrators, and there is no need of linear capacitors if we are able to work with signals related to charges.

Fig. 8. Measured spectrum (fi = 200 Hz, fs = 250 kHz). The ;r-axis has been normalized to the sampling frequency. Noise floor is located at —85 dB.

Fig. 9. SNDR with a sampling frequency of 250 kHz and an oversampling ratio of 32. The differences observed between the two modulators can be related with the different ratio between the metal input capacitor and the MOS reference capacitor ( 3 dB).

C. OTA Implementation

The integrators in the modulator have been implemented using gate capacitors and operational transconductance amplifiers with folded-cascode topology [21].

Practical implementations of SC circuits require high gain in order to insure sufficient linearity and parasitic insensitivity in the integrator response. An amplifier gain of 60 dB has proven to be adequate in high-resolution applications [7]. The specifications for the OTA were slew rate of 25 V/¿¿s and gain bandwidth of 10 MHz.

V. Test

The proposed modulator has been integrated in a standard single-poly, double metal 0.1-fim CMOS technology using device-level layout automation tools [22]. We have placed two identical interfaces in the same chip, a MOSFET-only version using floating MOSFET capacitors and a second one using metal capacitors. The active die area (excluding pads) is about 1.7 mm2. The digital circuits are physically separated from the analog section and are powered from a separate supply. Dummy capacitors, placed along the outside edge of the capacitor array, guarantee that the fringing fields at the periphery of the array are identical to those in the interior. Measurements were performed to determine the behavior of both modulators versus sampling frequency.

Fig. 8 shows the output spectrum of a 65536 samples bit stream. The result plotted in Fig. 9 show the absence of noticeable harmonic distortion in the floating MOSFET interface above the noise floor level.

The SNDR has also been obtained as

TABLE I

Resolution of Both Modulators

SNDR =

Signal

-^Noise ± -^Distorti«

Modulator Bias Voltage Resolution

Lineal ±2.5 > 14b

±1.65 > lib

Floating gate ±2.5 > 14b

± 1.65 > 10b

where Psignai, ^Noise, and PDistortion are the energy of the output signal, the noise floor, and the harmonic distortion. The results, corresponding to a bias voltage of ±2.5 V, are shown in Fig. 9. An SNDR of 14 bits has been measured for both modulators, this performance loss (we expected a resolution of 16 bits) can be due to two main reasons: a reduced output swing of the operational transconductance amplifiers (OTAs), and to analog nonidealities related with switches. The same test

Fig. 10. Response of the interface (i) without accelerometer (dashed line) (ii) with accelerometer (continuous line).

has been repeated biasing the system at ±1.65 V. The results for both tests are summarized in Table I.

Finally, we have connected an accelerometer to our interface and applied a unit step force equivalent to the electrostatic force generated by Vre{. This stimulus produces the output shown in Fig. 10.

To draw this plot, we have recorded the output of the modulator to calculate the mean value every 16 samples. We can see the behavior of the system when no acceleration is applied (dashed curve) and when an acceleration step is applied (continuous curve). In the first case the modulator goes to the steady point in 100 /xs. This time, is necessary to discharge the reference capacitor. In the second case, the curve is delayed due to the accelerometer response. Taking into account that the system goes to a steady position when the perturbation is applied, we can conclude that the system is strictly stable [23] and confirm the results of the proposed stability analysis.

VI. Conclusion

The feasibility of a FB interface based on a second-order AD modulator for capacitive sensors has been analyzed in order to

delimit the requirements that the modulator has to fulfill to assure system stability for a given set of constraints, or, on the other hand, to determine the range of sensors that can be used with a given modulator.

The proposed solution has been implemented using a modulator architecture based on charge integrators. It has been shown that charge integrators can be designed using gate capacitors.

The proposal has been validated comparing the results from two AS interfaces one with linear capacitors and one with MOS capacitors successfully developed in a standard 0.7-jum single-poly CMOS technology.

References

[1] N. Yazdi, F. Ayazi, and K. Najavi, "Micromachined inertial sensors," Proc. IEEE, vol. 86, no. 8, pp. 1640-1659, Aug. 1998.

[2] J. Chae, H. Kulah, and K. Najavi, "An in-plane high-sensitivity, low-noise micro-g silicon accelerometer," in Proc. IEEE Micro Electro Mechanical Syst. Conf. (MEMS'03), Kyoto, Tokyo, 2003, pp. 466-469.

[3] S. Rabbi and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. Boston, MA: Kluwer Academic, 1999.

[4] B. E. Booser and B. A. Wooley, "The design of sigma-delta modulation analog-to-digital converters," IEEE J. Solid-State Circuits, vol. SC-23, no. 6, pp. 1298-1308, Dec. 1988.

[5] T. Kajita, U. K. Moon, and G. Temes, "A two-chip interface for a MEMS accelerometer," IEEE Trans. Instrum. Measur., vol. 51, no. 4, pp. 853-848, Aug. 2002.

[6] Oversampling Delta-Sigma Converters: Theory, Design and Simula-tionJ. C. Candy and G. C. Temes, Eds. New York: IEEE Press, 1992.

[7] P. C. Maulik, M. S. Chadha, W. L. Lee, and P. J. Crawley, "A 16-bit 250-khz delta-sigma modulator and decimation filter," IEEE J. SolidState Circuits, vol. 35, no. 4, pp. 458-467, Apr. 2000.

[8] L. K. Baxter, Capacitive Sensors: Design and Applications. New York: IEEE Press, 1997.

[9] J. M. Gómez-Cama, O. Ruiz, S. Marco, J. M. López-Villegas, and J. Samitier, Simulation of a Torsional Capacitive Accelerometer and Interface Electronics Using an Analog Hardware Description Language. Southampton, U. K.: Computational Mechanics, 1997.

[10] M. Grigorie, "Integrated sigma-delta interface for capacitive sensors," Ph.D. dissertation, EPFL, Lausanne, Switzerland, 1994.

[11] H. Leuthold and F. Rudolf, "An ASIC for high-resolution capacitive microaccelerometers," Sensors Actuators A, vol. 21-23, pp. 278-281, 1990.

[12] K. Mochizuki, K. Watanabe, and T. Masuda, "A high-accuracy, highspeed signal processing circuit of differential-capacitive transducers," in Proc. IEEE Instrum. Measur. Technol. Conf., 1998, pp. 134-137.

[13] M. Lemkin and B. E. Booser, "A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 456-468, Apr. 1999.

[14] T. Ritoniemi, T. Karema, and H. Tenhunen, "Design of stable highorder 1-bit sigma-delta modulators," in Proc. IEEE Int. Symp. Circuits Syst., 1990, pp. 3267-3270.

[15] W. F. Lee, P. K. Chan, and L. Siek, "Electrical modelling of MEMS sensor for integrated accelerometer applications," in Proc. Electron Devices Meeting, Hong Kong, 1999, pp. 88-91.

[16] K. Dutton, S. Thompson, and B. Barraclough, The Art of Control Engineering. Reading, MA: Addison Wesley, 1997.

[17] M. Lemkin and B. E. Boser, "A three-axis micromachined accelerom-eter with a CMOS position-sense interface and digital offset-trim electronics," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 456-468, Apr. 1999.

[18] L. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 1057-1066, Dec. 1986.

[19] A. T. Behr, M. C. Schneider, S. N. Filho, and C. G. Montoro, "Harmonic distortion caused by capacitors implemented with MOSFET gates," IEEE J. Solid-State Circuits, vol. SC-27, no. 10, pp. 1470-1475, Oct. 1992.

[20] H. Yoshizawa, Y. Huang, P. F. Ferguson, and G. C. Temes, "MOSFET-only switched-capacitor circuits in digital CMOS technology," IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 734-747, Jun. 1999.

[21] K. R. Laker and W. M. C. Sansen, Design ofAnalog Integrated Circuits and Systems. New York: McGraw-Hill, 1994.

[22] M. Ingels and M. S. J. Steyaert, "Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode ICs," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1136-1141, Jul. 1997.

[23] H. Baher, Analog and Digital Signal Processing. New York: Wiley, 1994.