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0Ain Shams Engineering Journal (2015) xxx, xxx-xxx
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ELECTRICAL ENGINEERING
Extended SVM algorithms for multilevel trans-Z-source inverter
Aida Baghbany Oskouei a,% Mohamad Reza Banaei a, Mehran Sabahi b
a Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran b Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran
Received 25 October 2014; revised 18 March 2015; accepted 4 April 2015
KEYWORDS
SVM algorithm; Cascaded H-bridge multilevel trans-Z-source inverter; Accuracy;
Number of switching; THD
Abstract This paper suggests extended algorithms for multilevel trans-Z-source inverter. These algorithms are based on space vector modulation (SVM), which works with high switching frequency and does not generate the mean value of the desired load voltage in every switching interval. In this topology the output voltage is not limited to dc voltage source similar to traditional cascaded multilevel inverter and can be increased with trans-Z-network shoot-through state control. Besides, it is more reliable against short circuit, and due to several number of dc sources in each phase of this topology, it is possible to use it in hybrid renewable energy. Proposed SVM algorithms include the following: Combined modulation algorithm (SVPWM) and shoot-through implementation in dwell times of voltage vectors algorithm. These algorithms are compared from viewpoint of simplicity, accuracy, number of switching, and THD. Simulation and experimental results are presented to demonstrate the expected representations.
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1. Introduction
In recent years, multilevel inverters have received more and more attention because of their capability of high voltage operation, high efficiency and low electromagnetic interference (EMI) [1-5]. Multilevel inverter synthesizes a desired output
Corresponding author. Tel.: +98 9141186476. E-mail addresses: a_baghbany@azaruniv.edu (A. Baghbany Oskouei), m.banaei@azaruniv.edu (M.R. Banaei), sabahi@tabrizu.ac.ir (M. Sabahi).
Peer review under responsibility of Ain Shams University.
voltage from several levels of dc voltage sources as inputs. With increasing the number of dc voltage sources, the waveform of voltage output approaches a nearly sinusoidal waveform while using a fundamental frequency switching scheme [1].
Among all the switching algorithms proposed in the papers for multilevel converters, space vector modulation (SVM) seems most promising since it offers a great flexibility in optimizing switching pattern design and it is also well suited for digital implementation [5,6]. This control strategy works with high switching frequency and does not generate the mean value of the desired load voltage in every switching interval [5,6].
Despite the represented advantages, multilevel inverters output voltage amplitude is limited to dc sources voltage
http://dx.doi.org/10.1016/j.asej.2015.04.002
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This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
Figure 1 Trans-Z-source inverter structure.
Figure 2 Configuration of the cascaded H-bridge multilevel trans-Z-source inverter.
summation [2]. For the boost or buck of multilevel output voltage a dc/dc converter is needed. Z-source converter (ZSC) a novel power converter with both buck and boost capabilities first proposed in 2002 [7]. Operated in inverter mode, one of the salient features of ZSC is that the ac voltage can be controlled either higher or lower than the voltage limit imposed by a conventional voltage source inverter (VSI), giving a large degree of freedom to ac machine electromagnetic design and control [8,9]. Also, the quasi-Z-source inverter is a kind of improved topology based on Z-source inverter, is proposed in [10,11]. Recently, [12] proposes two current-fed trans-Z-source inverters that are capable of reaching wider voltage boost range and bidirectional power flow with a single diode. A wider output voltage range is essential to some applications such as HEV/EV motor drives. [13] uses the attractive advantages of quasi-Z-source cascaded multilevel inverter in
Figure 3 Configuration of the cascaded H-bridge 5-level trans-Z-source inverter.
application to photovoltaic (PV) power system, and analyzes modeling, impedance design, and efficiency of quasi-Z-Source module in cascaded multilevel photovoltaic power system. An effective control method, including system-level control and pulse width modulation (PWM) for quasi-Z-source cascade multilevel inverter based grid-tie photovoltaic (PV) power system is proposed in [14].
This paper proposes two new algorithms for multilevel trans-Z-source inverter. These algorithms based on SVM and employ cascaded H-bridge topology as a multilevel inverter combined with trans-Z-source inverter. Sections 2 and 3 present the working principle of extended SVM algorithms and finally, simulation results validate the algorithms and compare them.
2. Cascaded H-bridge multilevel trans-Z-source inverter
The trans-Z-source inverter structure is shown in Fig. 1. Trans-Z-source inverter operates in two modes: non-shoot-through and shoot-through state. With the analysis of circuit output voltage of trans-Z-network, vt is obtained as [12] follows:
1 -(1 + n)
B — -
1 -(1 + n) Tt
Table 1 Possible states of switches.
Voltage level
Output voltage
ON switches
Level 2 non-shoot-through) 2Vi S3, S4, S5, S6
Level 1 non-shoot-through) Vi Si, S3, S5, Sö
Level 1 shoot-through) Vi S1> ^ ^ ^ ^ S6
Level 1 non-shoot-through) Vi S3, S4, S5, S7
Level 1 shoot-through) Vi ^ ^ ^ ^ ^ S8
Level 0 non-shoot-through) 0 S3, S4, S7, Sg
Level 0 non-shoot-through) 0 Sb ^ ^ S7
Level 0 shoot-through) 0 Si, S2, S3, S4, S5, S7
Level 0 shoot-through) 0 S1, S3, S5, ^ S7, S8
Level — (non-shoot- —Vi Si, S3, S7, Sg
through
Level — (shoot-through) —Vi S1, S2, S3, ^ S7, S8
Level — (non-shoot- —Vi S1, S2, ^ S7
through
Level — (shoot-through) —Vi S1, S2, S5, ^ S7, S8
Level —2 (non-shoot-through)
Si, S2, S7, Sg
Figure 4 Space vectors for the 3, 5, 7, and 9-level inverters.
Figure 5 SVPWM method for shoot-through state control of trans-Z-source inverter.
Figure 6 Flowchart of shoot-through implementation in dwell times of voltage vectors algorithm in each H-bridge.
where T is period of switching, Tst is the total shoot-through state period, and B is boost factor.
During shoot-through time, the current of L2 is equal to current of C, and then the capacitor voltage decreases linearly. In other words, the capacitor is discharged by the transformer during shoot-through time. The capacitor value can be calculated as follows:
Il2 Tst
where IL2 is the average current of secondary of the transformer and DVC is the assumed voltage ripple of capacitor.
Fig. 2 shows the cascaded H-bridge multilevel trans-Z-source inverter. The output voltage is achieved by summing the output voltages of bridges:
Vo = Vol h-----h Von (4)
Each H-bridge can generate three different voltage outputs + V;, 0, — V;. The number of output voltage levels is 2 m +1 where m is the number of Z impedances or dc voltage sources [2].
This configuration, unlike the traditional multilevel inverters, has one extra shoot-through state (or vector) when the terminals of each H-bridge are shorted through both the upper and lower devices of any one leg or any two legs.
Fig. 3 shows the cascaded H-bridge 5-level trans-Z-source inverter and Table 1 indicates the values of Vo for possible states of switches. Because of two number of dc sources in each phase of this topology, it is possible to use it in hybrid renewable energy.
Figure 7 Voltage waveforms in B = 1; (a) output voltage of trans-Z-network; (b) capacitor voltage; (c) load voltage; (d) load current; (e) harmonic spectra of load voltage; and (f) harmonic spectra of load current.
3. Proposed SVM algorithms
Any three-phase quantities, e.g., three-phase voltages or currents can be represented by a space vector in d-q plane via Park's transformation. The vector starts from the origin and ends at a certain point so that the length and phase angle of vector together represent the instantaneous values of particular three-phase quantities. If the three-phase quantities are sinusoidal functions of time and are symmetrical, the vector will be rotating at a constant angular velocity with a constant length and, so, the locus of vector forms a circle. In other words, a rotating voltage vector can represent three-phase sinusoidal voltages mathematically. If the three-phase quantities are not symmetrical, the Park's transformation gives not only d and q components, but also a zero-sequence component that is the mean value of three-phase quantities [1,15]. Fig. 4 shows space vectors for the 3, 5, 7, and 9-level inverters [5].
This control method is based on the voltage vector generated by the inverter, defined as [5,6] follows:
V(t) = 3 [van (t)
-avBN(t)+a2VcN(t)]
where vAN, vBN, and vCN are the voltages of terminals A, B and C with respect to the neutral N and a is the complex operator. Considering the cascaded H-bridge 7-level inverter with 3 cells per phase, each phase can generate 7 different voltages. The
representation of the voltage vectors in the complex plane considers that:
v(t) = vd + Jv„
where vd and vq correspond to the components of v(t) in the d and q axes, respectively. These components are given by following:
Vd = 3 (2van - vbn - vcn) Vq = p (vbn - vcn)
The Cartesian coordinate system can be transformed to a 60° coordinate system as below:
va — v cos 6--— sin 6
Table 2 System parameters.
Vdc 100 v
C 2100 iF
Nominal frequency 50 Hz
Load resistance 100 X
Load inductance 26 mH
Carrier frequency in SVPWM algorithm 1 kHz
Figure 8 Voltage waveforms in B = 1.25 for SVPWM algorithm; (a) output voltage of trans-Z-network; (b) capacitor voltage; (c) load voltage; (d) load current; (e) harmonic spectra of load voltage; and (f) harmonic spectra of load current.
Figure 9 Voltage waveforms in B = 1.25 for shoot-through implementation in dwell times of voltage vectors algorithm; (a) output voltage of trans-Z-network; (b) capacitor voltage; (c) load voltage; (d) load current; (e) harmonic spectra of load voltage; and (f) harmonic spectra of load current.
Figure 10 Voltage waveforms in B = 1.66 for SVPWM algorithm; (a) output voltage of trans-Z-network; (b) capacitor voltage; (c) load voltage; (d) load current; (e) harmonic spectra of load voltage; and (f) harmonic spectra of load current.
2v . = —ffiffi Sin h л/3
where va and vß are the coordinates of a space vector v in the 60° coordinate system, and v and h are its amplitude and phase angle, respectively.
The SVM can be implemented by the following steps [16]:
Step 1. Determine vd, vq, v, and h.
Step 2. Determine dwell time of related vectors Tb T2, and To.
Step 3. Determine the switching time of each switch.
In this paper, SVM algorithm is used for modulation of cascaded H-bridge multilevel trans-Z-source inverter. The shoot-through state can be implemented through different methods. In this section, two algorithms are defined as below:
3.1. Combined modulation algorithm (SVPWM)
This algorithm combines space vector modulation (SVM) and pulse width modulation (PWM) methods, named SVPWM. Fig. 5 illustrates SVPWM method for shoot-through state control of trans-Z-source inverter. This method employs two extra straight lines as shoot-through signals, VSC and — VSC. When the carrier triangular signal is greater than VSC or it is smaller than — VSC, the related H-bridge turns into shoot-through state.
In this algorithm, for each H-bridge of phase, a carrier signal is assumed. Fig. 5 leads as follows:
Tst. T
where T1 is shoot-through time during quarter of carrier period time, Tca. It is clear that
Va - Vsc
where Vca is the peak value of carrier signal.
So, substituting (10) and (11) into (2), boost factor is obtained as follows:
B =-t1-r (13)
1-2'" " N
3.2. Shoot-through implementation in dwell times of voltage vectors algorithm
This algorithm employs dwell times of voltage vectors and implements shoot-through state in zero states in each H-bridge. It deals with time ration of implementation shoot-through state to dwell times, which known as Rst. Indeed, Rst is a number that determines duty cycle of
Figure 11 Voltage waveforms in B = 1.66 for shoot-through implementation in dwell times of voltage vectors algorithm; (a) output voltage of trans-Z-network; (b) capacitor voltage; (c) load voltage; (d) load current; (e) harmonic spectra of load voltage; and (f) harmonic spectra of load current.
the condition pulse. This algorithm investigates shoot-through facility in each H-bridge and implements shoot-through state in it base on Rst. In other words, shoot-through implementation of each H-bridge is done in specified percent of the feasible times. So, according to flowchart of Fig. 6, shoot-through implementation in this algorithm is based on two conditions: (1) shoot-through facility in each H-bridge, (2) being 1 of condition pulse base on Rst. Then, this method does not increase switching number significantly, due to lack of forced zero. But in it, Tst cannot be determined accurately. Although increasing time ratio of implementation shoot-through state to dwell times causes Tst to increase. But, this algorithm is not linear. In other words
T1 = /(Rst) (14)
where /(Rst) > 0. Also
Tt < Rst (15)
So, it is necessary to estimate this nonlinear relation based on numerical data.
4. Results
4.1. Simulation results
Simulations have been performed to prove the capabilities of represented SVM algorithms and comparison of them for control of cascaded H-bridge 7-level trans-Z-source inverter. The system parameters are listed in Table 2.
Three different boost factors have been considered, i.e. 1, 1.25, and 1.66.
Fig. 7 shows voltage waveforms in B = 1. Fig. 7(a) presents output voltage of trans-Z-network v, which is about 100 V. Capacitor voltage, load voltage, load current, and harmonic spectra of them are displayed in Fig. 7(b-f). All THDs in this paper are calculated up to 20th harmonic.
Figs. 8 and 9 present related voltage waveforms of two algorithms in B = 1.25. For this boost factor, VSC is considered 0.9, where Vca = 1 in SVPWM algorithm, and Rst = 0.35 in shoot-through implementation in dwell times of voltage vectors algorithm. From these figures it is evident that vi is almost 125 V. With attention to THD of voltage in two algorithms, it is obtained that THD of second algorithm
Figure 12 Experimental results in B = 1.25; (a) output voltage of trans-Z-network; (b) load voltage.
is lower than first algorithm, significantly. Although fundamental of these voltages is not extremely different. From these figures it can be observed that frequency of second algorithm is lower than first algorithm.
The other boost factor is 1.66 and its voltage waveforms are displayed in Figs. 10 and 11, where VSC = 0.8 and Rst = 0.54 in first and second algorithms, respectively. In these figures, Vi is almost 166 V. Despite vt is high frequency in first algorithm;
Figure 13 Simulation results of Proposed Inverter with Experimental Prototype Parameters in B = 1.25 (PWM algorithm); (a) output voltage of trans-Z-network; (b) load voltage.
Figure 14 Simulation results of Proposed Inverter with Experimental Prototype Parameters in B = 1.25 (SVPWM algorithm); (a) output voltage of trans-Z-network; (b) load voltage.
it is low frequency in second algorithm due to increase switching numbers in this algorithm, significantly. Load voltage also has low THD in second algorithm, although the fundamental is the same, approximately.
- (a) rvWVT TU^vr TWi rmwvr fum T|U
0.95 0.96 0.97 0.90 0.99 1
Time (s)
40 I-1-1-1-1-
0.95 0.96 0.97 0.98 0.99 1
Time (s)
Figure 15 Simulation results of Proposed Inverter with Experimental Prototype Parameters in B = 1.25 (shoot-through implementation in dwell times of voltage vectors algorithm); (a) output voltage of trans-Z-network; (b) load voltage.
4.2. Experimental results
Cascaded H-bridge 5-level trans-Z-source inverter was built using IRFP460 MOSFETS as the switching devices and MUR860G as fast diodes. Two 12 V dc voltage sources were used to individually supply of each trans-Z-network. Trans-Z-networks consist of 4700 pF capacitors. The switching signals which were obtained from PWM algorithm, were produced with PCI-1716 DAQ for B = 1.25. The switching signals were interfaced to the inverter power switches through optocoupler isolators TLP250. The photograph of the prototype components is displayed in Fig. 12(a). Load in this experimental is 20 + 300 J O.
For B = 1.25, the output voltage of trans-Z-network is shown in Fig. 12(b). As observed, the levels of vi are approximately 0, 15 V, where compared to dc voltage source, the amplitude of voltage is boosted according to B = 1.25. The load voltage is shown in Fig. 12(c). Measured five levels are approximately 0, ±15, ±30. As it can be seen, the results verify the ability of proposed inverter in voltage boosting and generation of desired output voltage waveform.
4.3. Simulation ofproposed inverter with experimental prototype parameters and comparison of them
Some simulations have been performed to compare simulation and experimental results in this section. So, proposed inverter with experimental prototype parameters which represented in previous section. Fig. 13 shows the simulation results. From comparison of Figs. 12(b) and (c) and 13(a) and (b), similarity of the figures is evident.
Also, extended SVM algorithms are applied to this cascaded H-bridge 5-level trans-Z-Source inverter, and the results of them are presented in Figs. 14 and 15.
5. Conclusion
In this paper two extended SVM algorithms have been proposed, that employ cascaded H-bridge multilevel trans-Z-source inverter. Among these algorithms, combined modulation algorithm (SVPWM) is simple and has mathematical base, so it is accurate. But in shoot-through implementation in dwell times of voltage vectors algorithm, the calculation of relation between total shoot-through state time and implemented shoot-through ratio to dwell times is difficult. Although, this algorithm causes decrease in THD of voltage waveform. In addition, it does not increase switching number significantly, unlike SVPWM algorithm.
Acknowledgment
This research has been supported by Azarbaijan Shahid Madani University.
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Aida Baghbany Oskouei was born in Tabriz, Iran in 1988. She received the B.Sc. degree in electrical engineering from Azarbaijan Shahid Madani university, Tabriz, Iran in 2010 and the M.Sc. degree in electrical engineering from the university of Tabriz, Tabriz, Iran, in 2012. She is currently working toward the Ph.D. degree in electrical engineering at Azarbaijan Shahid Madani university. Her current research interests include modeling and application of power electronic circuits in power systems and renewable energies.
Mehran Sabahi was born in Tabriz, Iran, in 1968. He received the B.S. degree in electronic engineering from the University of Tabriz, the M.S. degree in electrical engineering from Tehran University, Tehran, Iran, and the Ph.D. degree in electrical engineering from the University of Tabriz, in 1991, 1994, and 2009, respectively. In 2009, he joined the Faculty of Electrical and Computer Engineering, University of Tabriz, where he was an Assistant Professor from 2009 to 2013 and where he has been an Associate Professor since 2014. His current research interests include power electronic converters and renewable energy systems.
Mohamad Reza Banaei was born in Tabriz, Iran. He received his M.Sc. degree from the Poly Technique University of Tehran, Iran, in control engineering in 1999 and his Ph.D. degree from the electrical engineering faculty of Tabriz University in power engineering in 2005. He is an Associate Professor in the Electrical Engineering Department of AzarbaijanShahidMadani University, Iran, which he joined in 2005. His main research interests include the modeling and controlling of power electronic converters, renewable energy, modeling and controlling ofFACTS and Custom Power devices and power systems dynamics.
