Scholarly article on topic 'Gate stack technology for nanoscale devices'

Gate stack technology for nanoscale devices Academic research paper on "Materials engineering"

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Abstract of research paper on Materials engineering, author of scientific article — Byoung Hun Lee, Jungwoo Oh, Hsing Huang Tseng, Rajarao Jammy, Howard Huff

Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.

Academic research paper on topic "Gate stack technology for nanoscale devices"

Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.

Byoung Hun Lee*1, Jungwoo Oh, Hsing Huang Tseng2, Rajarao Jammy1, and Howard Huff

SEMATECH, 2706 Montopolis Drive, Austin, Texas, USA 1IBM assignee, 2Freescale assignee *E-mail: Byoung.Hun.Lee@SEMATECH.org

Over the last four decades, the performance of the modern CMOS device has been improved primarily by physical scaling. In particular, gate oxide and junction depths have been scaled together with gate length to avoid the short channel effects (SCEs) that accompany physical scaling. In this sense, gate stack technology is one of the key drivers in enhancing the performance of semiconductor devices.

Gate oxide thickness has been scaled approximately 0.75 times in each technology generation, assuming a three-year cycle per technology node (Fig. 1)1. Recently, however, the thickness of the gate oxide has scaled more slowly than the historical pace. An equivalent

oxide thickness (EOT) of ~1 nm has been used for the past two to three generations because of issues such as process controllability, high leakage current, and reliability limits, signaling an end to the scaling era and the advent of a new era of material and device evolution.

Although scaling of the gate oxide has slowed down, the performance of CMOS devices has been improved continuously by controlling the transport properties of channel electrons using strain applied to Si channels2-5, more precise control of short channel devices combined with multiple spacers to form shallow, intermediate, and deep junction areas, and more forgiving circuit technology. While these

32 materials june 2006 | volume 9 | number 6

ISSN:1369 7021 © Elsevier Ltd 2006

Publication year

Fig. 1 Scaling trend of gate oxide thickness over the past five technology generations from the 0.18 ^m to 65 nm node. Experimental data (Lgate) and equivalent oxide thickness (EOT) are collected from device papers presented at conferences. Projected values are based on the 2005 International Technology Roadmap for Semiconductors (ITRS). When only inversion oxide thickness (Tinv) is provided in the literature, 8 A is subtracted from Tinv to account for the additional capacitance component resulting from the poly depletion effect at the gate side and the quantum mechanical effect at the channel side.

approaches, in conjunction with gate length scaling, have enhanced device performance in recent technology nodes at the same traditional scaling rate as shown in Fig. 1, SCEs have inevitably degraded and become a major barrier for performance enhancement in future technology generations.

Since the benefits of strain engineering are limited in extremely scaled devices, properly scaled gate stacks or alternative device structures, such as multigate FETs (MUGFETs), will be necessary for the next technology generations. We review recent developments in gate stack technology in conjunction with potential device and material solutions to provide an overview of current technologies and the challenges ahead of us.

Overview of alternative gate stack technology

The demise of SiO2 scaling has been predicted since the 1980s. The increasing gate leakage current as a result of the direct tunneling current is the culprit. To reduce the tunneling current, the physical thickness of the gate dielectric has to be increased beyond the tunneling limit. Thus, dielectric materials with dielectric constants higher than SiO2 have been proposed as a possible solution.

In the 1980s, CeO2 and Y2O3 were studied to replace gate oxides with an EOT of ~6 nm6-9. However, most of the high-k dielectrics demonstrated severe crystallization-induced leakage currents and poor reliability in the thick EOT regions. Research on high-k dielectrics was phased out as nitrided SiO2 was successfully implemented.

In the mid-1990s, interest in high-k dielectrics was renewed. Early work on alternative gate dielectrics focused on TiO2, Ta2O5, and BaSrTiO3, which were inherited from dynamic random access memory

(DRAM) capacitor dielectric research at that time10-15. Research on high-k dielectrics quickly converged on the Al2O3, HfO2, and ZrO2 family, which has a band gap larger than 5.0 eV16-21. While HfO2 and ZrO2 received most attention in the late 1990s, based on their better thermal stability with Si22-24, it should be noted that several publications addressed HfO2 and ZrO2 as early as the 1970s25-27. Wilk et al.28 provide a more thorough review of research during this time.

Because of thermal stability issues when in contact with a polySi gate29, high-k dielectrics were often studied with metals such as Pt or Al. Thus, it took some time to discover that the effective work function (EWF) of a polySi gate could not be altered easily by doping when it was used with high-k dielectrics. This is primarily because the EWF of a polySi/high-k dielectric stack is determined by Si-Hf bonding instead of the Fermi level of the polySi gate30. This problem is often called 'Fermi-level pinning' because the EWF of polySi is fixed at a certain point near the Si conduction band edge. As a result, PMOS devices with a polySi/high-k stack have a very high threshold voltage Vth beyond the practical range. This can be relieved using high-k materials with a pinning point close to the Si valence band edge, which is favorable for PMOS. Al2O3 capping has been proposed, but the usable range of EWF is limited31-33.

This phenomenon has posed a serious challenge in the implementation of high-k dielectrics because to obtain the best performance in CMOS devices, the effective work function of NMOS and PMOS should be close to the conduction (Ec ~ 4.05 eV) and valence (Ev~ 5.15 eV) bands, respectively34. The reduced adjustable EWF range of polySi/high-k stacks limits their use to low-power applications where the requirement for threshold voltage is not as strict as it is in high-performance devices. Dual work function metal

electrodes with EWFs close to Ecand Evare needed for highperformance applications. But it has been found that even metal electrode materials suffer from a limited EWF range when combined with high-k dielectrics. The following sections give more details of dielectric and electrode developments.

Advances and challenges in dielectric development

Hf-based oxides, including HfO2 and HfSiOx have emerged as promising candidates for high-k dielectrics because of their excellent thermal stability with Si. Furthermore, the mobility of HfSiON devices has improved significantly35, almost matching that of nitride oxide at an EOT of ~1 nm. The two key breakthroughs that have enabled this mobility enhancement are understanding of transient charging behaviors in high-k devices36-40 and scaling of high-k thickness below the tunneling limit to eliminate residual tunneling carriers in the high-k layer41,42. By keeping the thickness of the high-k layer below 2 nm, mobility degradation arising from transient charging effects can be eliminated. The high-field mobility value versus EOT curve clearly demonstrates this observation (Fig. 2).

Thinning of the high-k layer, however, is only a temporary measure that works for a limited range of EOTs and leakage currents. Low standby power (LSTP) applications require a very low leakage current. To meet LSTP targets, the high-k thickness must be increased without degrading the mobility. Careful optimization of the bottom oxide and Hf-silicate composition is necessarytomeettheserequirementsfor LSTP applications.

For high-performance applications, more aggressive EOT scaling is needed. Physical scaling of the HfSiON layer is limited to an EOT of ~0.9 nm to keep mobility above 85% of the universal curve43. Thus, to scale the EOT of the total stack, the interfacial oxide layer should be further optimized. Scaling the interfacial layer, however, imposes serious limitations on the process window, in terms of the applicable high-k layer and heat cycle, and the mobility decreases rapidly as the thickness of interfacial layer is scaled as shown in Fig. 2.

Fig. 3 shows the simulated high field mobility as a function of interfacial oxide. The thickness of HfO2 is fixed at 30 A and only optical phonon scattering is includedinthecalculation.Whenan interfacial oxide is thinner than 0.9 nm, the impact of optical phonon scattering44 on the channel carrier mobility increases rapidly. Remote charge scattering45 is not includedinthiscalculationbecausethe magnitude of remote charge scatteringcanbestronglyaffectedbythe quality of the high-k layer.

To avoid the trade-off between EOT scaling and mobility, it is important to (1) eliminate the chargescatteringsourcewithinthe high-k layer using elaborate passivationprocesses45-49 and(2)increase the dielectric constant of the interfacial oxide with a minimal impact on the interface state density50.

While HfSiON can be used for the 45 nm and 32 nm generations, any further extension of high-k dielectrics will require materials with a dielectric constant higher than HfO2. Lanthanide oxides have been proposed as higher-k materials, but many of them show degraded dielectric characteristics compared with Hf oxides51,52. An alternative path to future scaling is to use channel materials other than Si. For

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Fig. 2 Scatter chart of high-field mobility (1 MV/cm) versus EOT for various high-k devices fabricated at SEMATECH. Filled square data are obtained from devices with high-k dielectrics thicker than 30 A, while open circle data are obtained from devices with high-k dielectrics thinner than 25 A. The reference line represents 90% of SiOz universal mobility at 1 MV/cm, which is close to the high-field mobility of heavily nitrided oxides used in the 90 nm technology node. Three reference data points are also shown with star symbols.

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example, the formation of interfacial oxide can be suppressed when a high-k dielectric is deposited on Ge or GaAs substrates53-55. While the quality of the interface may be compromised with these channel materials, the scalability of the high-k dielectric stack will be enhanced. The challenges in this path are to overcome the problems associated with the degraded interface and to make use of the benefits of high carrier mobility in Ge or other channel materials. If Hf-based oxides can be successfully implemented with these channel materials, Hf-based oxides might then be usable beyond the 32 nm node.

Advances and challenges in electrode development

As mentioned above, the application of polySi/high-k stacks are limited by Vthcontrollability, poor reliability, dopant penetration, and inversion oxide thickness Tinv scalability. Thus, n- and p-type polySi gates must be replaced by metal electrode materials with suitable EWFs close to Ec and Ev of the Si substrate.

One technical challenge in metal electrode research is that the vacuum work function values of metalsarenotdirectlycorrelatedto the Vth of devices because of:

• Dipole formation resulting from charge transfer between metal atoms and dielectric atoms56;

• Interface mixing during CMOS processing57;

• Oxygen redistribution acrossthemetal/high-k interface58;

• Formation of interface defects and charge redistribution around the defects;

• The effect of impurities59; and

• Localized compositional variations in electrode materials60.

Thus, overall electrode processes, such as the deposition method, heat

cycle, and dielectric composition, need to be optimized together to develop a well-defined metal electrode process.

While many of the factors listed above are not well understood for most materials, the EWF of metals on certain sets of dielectrics can be studied as a first step toward overall gate stack optimization. Fig. 4 shows the EWFs of extensive metal systems studied at SEMATECH. Data included in Fig. 4 were obtained using an oxide thickness series formed on a single substrate to minimize variations in interface charge. To study the change in EWF at the metal/high-k interface, very thin HfSiON layers were deposited on a terraced oxide wafer61. The x-axis represents the material systems and two groups of data points show EWFs obtained with two different gate dielectrics (SiO2 and HfSiOx). The difference in EWF between SiO2 and HfSiOx is often explained by dipole formation, i.e. if the EWF of the metal is smaller than the charge neutrality level (CNL) of the underlying dielectric, charge can be donated to the dielectric side and the EWF is shifted toward the midgap value (-4.6-4.7 eV)62. When the EWF is higher than the CNL of the underlying dielectric, the EWF is shifted upward. As a result, the electrode EWF on the high-k dielectric should show a smaller range than on SiO2. However, experimental data shown in Fig. 4 indicate that the EWF shift because of dipole formation is actually unidirectional, indicating that dipole formation is more affected by metal-oxide bonding and microscopic charge transfer than the CNL of the underlying dielectric.

Several metal systems show EWF values near the conduction and valence band edge of Si, even after high temperature processing. These satisfy the requirements for gate-first CMOS integration, namely that the EWF of the electrodes should be close to EcSi for NMOS and Ev,Si for PMOS after the CMOS heat cycle, which is typically a 1100°C spike

Fig. 4 Effective work function (EWF) of metal electrode materials on SiOz and HfSiON extrapolated from flatband voltage (Vfb)-EOT curves, sorted in order of EWF value of metal systems on SiO2. Vfb values are measured using terraced oxide structures after a 1000°C 5 s anneal61.

anneal or a 1000°C 5 s rapid thermal anneal. The metal electrode systems are not specified in Fig. 4 because the EWF of the metal/ high-k stack can be controlled by many factors described above and, in fact, the electrode and high-k dielectric is best considered as a single material system that requires simultaneous optimization.

Once thermally stable metal electrodes with band-edge EWFs have been identified, the next challenge is to obtain a low Vth that matches the EWF values. Since the Vth of the actual device may be affected by additional factors, such as EOT, reactions with gate etch process gases, mixing with capping materials, and oxygen redistribution from the sidewall63,64, it is not straightforward to predict Vth from the flatband voltage Vfb. Fig. 5 compares EWF values calculated from a Vb-EOT curve with those determined using the Vth of a MOSFET. In the

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Fig. 5 Correlation between EWF values extracted from Vp-EOT curves of terraced oxide capacitor wafers (x-axis) and EWF values extracted from the Vth of transistor wafers (y-axis). In an ideal case, EWF values from Vfb and Vth should match each other for the same material system, but deviations are observed in the high work function region (EWF ~ 5.0 eV) because additional factors affect the Vth values.

MOSFET case, the Vth of a TiN gate MOSFET is used as a reference for the EWF and the difference between the Vtb of TiN gate MOSFETs and other metal electrodes is used as the difference in the EWF.

Fortunately, the correlation between Vfb and Vth is reasonable for the conduction band side (close to 4.0 eV). On the other hand, as the EWF increases, the deviations between Vfb and Vth appear to increase. This result is more clearly shown in Fig. 6, where Vfb versus EOT curves show a strong roll-off at EOTs less than 2.5 nm. Roll-off of the Vfb curve in the low EOT region can be explained by several mechanisms, such as bulk charge generation arising from the diffusion of electrode species or stronger dipole formation in thinner EOT regions resulting in a dielectric-thickness-dependent EWF change. This roll-off characteristic is strongly dependent on the high-k dielectric

Fig. 6 Vfb-EOTcurve for a typical n-metal electrode (EWF ~ 4.0 eV) and a p-metal electrode (EWF ~ 5.1 eV). The high EWF electrode shows a Vfb roll-off toward a midgap EWF as the thickness of the capacitor dielectric is reduced, indicating the influence of an extrinsic reaction limiting the EWF in the thin EOT region.

thickness and metal electrode composition. To obtain a high EWF of ~5.0 eV, Vfb roll-off should be minimized, especially in the EOT < 1 nm region.

Silicides are another group of materials being investigated for metal electrode applications. Fully silicided (FUSI) gates have received a lot of attention because the polySi gate can be silicided with a relatively low heat cycle and minimal damage to the gate dielectric after device fabrication. CoSi2 was used in the initial demonstration of a silicided gate65, but the focus quickly shifted to NiSi and NiSi3 because the work function of Ni silicides can be modified with dopants in the polySi gate or a phase of Ni silicides66-69. However, the EWF range with a silicide gate is still limited, even though the FUSI process only uses low-temperature steps. Various silicideshavebeenstudiedtofind a gate showing a band-edge EWF. The most promising silicide gate materials are HfSi (~4.2 eV)70 and ErSi (~4.2 eV) for NMOS and PtSi (~4.9 eV) for PMOS71. Even though the range of EWF is not wide enough for high-performance applications, these silicide gates can still be used in low-power applications or applications requiring quarter gap electrodes (~4.3 eV for NMOS and ~4.8 eV for PMOS), such as FinFETs or fully depleted silicon-on-insulator (FDSOI) devices72. There are several potential challenges in the FUSI approach, such as pattern-dependent silicidation73 74, strain control arising from volume expansion, and process complexity for a dual-silicide approach.

Once electrode materials have been chosen for each application, the impact of reliability should be studied in detail. Metal electrodes can affect the reliability of gate dielectrics in many ways: diffusion and intermixing with the dielectric, oxygen, and nitrogen redistribution, and impurity contamination. None of these topics has been well investigated, primarily because the material systems have not been finalized yet.

Fig. 7 shows an example of the influence of metal electrodes on the underlying dielectric, SiO275. Interface trap density Dt measured by a conductance method is degraded by metal diffusion or oxygen redistribution in the interfacial oxide layer, especially for more reactive electrodes such as TiAlN or TiSiN. As the metal/stacks are more aggressively scaled, the reaction between metal electrode and gate dielectric will be aggravated and limit the material choices. Thus, future gate stacks that use metal electrodes may need a stronger passivation process, such as a high-pressure hydrogen anneal.

Fig. 8 shows that the degradation in mobility caused by a reactive metal electrode can be recovered with a high-pressure anneal75. Electrodes with more reactive compositions (Ti-rich TiSiN) degrade the mobility more significantly, and the recovery rate after a high-pressure anneal is higher than for other electrodes. This result agrees with the increased Dit shown in Fig. 7, which can be attributed to Si dangling bonds formed by oxygen vacancies at the interface. This example shows that the degradation mechanisms of metal electrode/high-k dielectric devices will be quite different from those of polySi gate/SiO2 devices, and novel reliability characterization methods or passivation

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Fig. 8 Ratio of mobility (^) recovery before and after high-pressure hydrogen annealing. Mobility degradation arising from the metal electrode/3 nm HfO2 reaction can be recovered by hydrogen passivation, indicating that the increased Dit shown in Fig. 7 likely originates in Si dangling bonds.

processes will be required. Even though enormous efforts have been invested and significant progress has been made, considering the complexity of reliability qualification, implementing metal/high-k technology remains a challenge.

Gate stack technology for the 22 nm node and beyond

Beyond the 22 nm node, where gate lengths will become less than 10 nm, it is still controversial whether planar CMOS devices will be a practical option because of dopant fluctuations, control of SCEs, and other problems. Multigate MOSFETs such as FinFETs or double-gate MOSFETs may provide better electrostatic control, but these devices have their own limitations in terms of actual device fabrication.

Nanotubes or nanowires provide other types of devices, promising more current drivability at the single device level76. However, these devices have not demonstrated a performance gain at the product level. Thus, there is a strong motivation to continue scaling planar devices but with higher channel carrier mobility using various high transport channel materials such as Ge, GaAs, etc.77. Table 1 illustrates the potential evolution paths of gate stack technology. Beyond the 22 nm node, non-Si channel materials are likely to be needed to continue the device scaling trend. In Table 2, the material characteristics of several potential channel materials are listed. Ge, InP, and GaAs have smallest number of technical challenges among the many alternative channel materials. Ge and GaAs, in particular, are actively investigated, and MOSFETs have been demonstrated already. In this section, challenges associated with gate stacks on these novel channel materials are described.

Ge MOSFETs

Of all the semiconductor materials, Geoffersthegreatestpotentialfor integration into Si CMOS technologytoachievehighmobility.Ithas a bulk hole mobility four times higherthanSi78 and,consequently,Ge-channel MOSFETs have been studied for decades79,80.

Even though its mobility-related advantages are apparent, Ge technology has not been widely deployed primarily because Ge surfaces are not effectively passivated with Ge oxides. The unstable Ge oxides can induce point defects at the interface. Study of Ge oxidation has shown thermal decomposition of GeO2 into Ge suboxides (GeOj81-87. One of suboxides, GeO, thermally desorbs from the Ge surface at low temperatures (~450°C) even at atmospheric pressure, which results in the loss of the Ge surface.

Research on Ge MOSFETs,therefore,hasfocusedonthe development of a reliable gate oxide.ManyGeMOSFETshavebeen demonstrated using high-k gate oxidessuchasgermaniumoxynitride, Al2O3, ZrO2, and HfO254,88-99. However, Ge diffusion into high-k dielectrics during thermal processes and its reaction at the interface to form interfacial GeOxare found to be major problems. Interestingly, one study showed that a ZrO2 gate stack is more stable on Ge than HfO2 because there is less intermixing100. The plasma surface passivation and use of an interfacial AlN layer between HfO2 and Ge

Table 1 Gate stack technology trends for future semiconductor technology nodes. Italicized options signify secondary priority.

32 nm Technology node 22 nm 16 nm 11 nm

Substrate Si Si non-Si non-Si Si

Device Planar Planar Nonplanar Nonplanar Planar Nonplanar

High-k dielectric Hf-based Hf-based Non-Hf- Non-Hf-based Hf-based Non-Hf-based

Interfacial layer SiO2 SiO2 Non-SiO2 SiO2 Non-SiO2

improves device characteristics by suppressingtheformationofGeO. The lowest EOT achieved with a Ge MOS capacitor91 is 5.6 A. The lowest Dt of 8 x 1011 - 1 x 1012 cm-2 eV-1 with an EOT of 7.5 A was obtained with a Ge MOSFET93. As mentioned above, EOT scalability of Ge channel MOSFETs (<5 A for the 22 nm node) is good, but the interface quality should be improvedfurthertoachievehigher performance.

GaAs MOSFETs

Heterostructures of III-V semiconductors have been widely used in the fabrication of heterojunction bipolar transistors (HBTs), metal-semiconductor field-effect transistors (MESFETs), high electron mobility transistors (HEMTs), and optoelectronic devices. High carrier mobility and direct band gap characteristics have been a major motivation for the use of III-V semiconductors in such applications101-113. Recently, III-V semiconductors have been studied as an alternative channel material for MOSFET technologies. There are several advantages to III-V MOSFETs over other types of III-V devices such as MESFETs, HEMTs, and HBTs. Surface channel MOSFETs, which control carrier transport using inversion charges, have much lower off-stage currents than other types of device that transport majority carriers in the buried channel.

The major technical challenge in the development of GaAs MOSFETs is again a gate oxide. Like Ge, the native oxide of GaAs does not show good passivation characteristics. The lack of a good

Table 2 Material characteristics of alternative channel materials. Highlighted cells indicate that there are significant

technical challenges to build MOSFETs with these materials.

Si Ge GaSb InN InP GaAs InAs InSb

Band gap (eV) 1.11 0.67 0.726 0.7 or 1.9? 1.34 1.43 0.354 0.17

Breakdown field (MV/cm) 0.3 0.1 0.05 1.2 0.5 0.06 0.04 0.001

Electron mobility (cm2/V.s) 1350 3900 3000 < 3200 5400 8500 40 000 77 000

Hole mobility (cm2/V.s) 480 1900 1000 < 80 200 400 500 850

Thermal conductivity (W/cm.K) 1.3 0.58 0.32 0.45 0.68 0.55 0.27 0.18

Lattice constant (Ä) 5.43 5.66 6.09 3.533 5.87 5.65 6.06 6.48

3s materials june 2006 | volume 9 | number 6

passivation oxide results in a high gate leakage current and high surface state density. It is known that the native oxide of GaAs induces Fermi-level pinning and high D;t114-118. The Fermi level of GaAs is pinned at the oxide-substrate interface with a Ditas high as ~1013 cm-2 eV-1.

GaAs MOSFETs have been demonstrated using a variety of gate dielectrics such as SiO2, Al2O3, Ga2O3(Gd2O3), InAlP oxide, and AlGaAs oxide56,119-128. For InAlP and AlGaAs oxides, the lattice-matched epitaxial InAlP and AlGaAs layers are oxidized in situ to form a gate oxide129. Of the proposed alternative gate dielectrics for GaAs MOSFETs, an epitaxially grown Gd2O3 film seems to show the lowest interface state density, with Dt < 1010 cm-2 eV-1 for both the inversion channel and the depletion-mode GaAs MOSFETs130-132. However, this work showed that low Dit values result from 90 A thick Ga2O3(Gd2O3) gate dielectrics, and the electrical characteristics of the gate dielectric itself were not reported. Thus, for GaAs MOSFETs, EOT scalability (<5 A for the 22 nm node) is still a significant challenge.

Nanowire devices

Nanowire devices have been investigated with the aim of achieving better gate control, for example in surrounded gate devices76,133,134. Various materials such as Si, Ge, GaAs, and carbon nanotubes (CNTs) have been studied for nanowire MOSFETs135-138. CNTs in particular provide a unique opportunity to use deposited gate oxides because

CNTs have naturally low interface states, while other nanowire devices have gate stack compatibility problems as in the equivalent planar devices. Very well behaved devices are reported with 8 nm ZrO2 on CNT139 and 20 nm HfO2 on CNT140. Since CNT MOSFET studies are in an initial phase, relatively thick high-k dielectrics are used for demonstration purposes and the electrical characteristics of the gate dielectric itself are not reported. In this case, basic characterization techniques for CNT devices will need to be explored to define capacitance-voltage (C-V), mobility, or interface states.

Conclusion

In this article, the current status and challenges associated with alternative gate stack technology have been briefly reviewed. Considering the progress of technology development, an alternative gate stack with a metal gate/high-k dielectric will be implemented for Si-based technology in the near future. However, research on metal gate/high-k dielectric technology for non-Si channel materials such as Ge, GaAs, or CNT has been so limited that it will become a gating factor for future technology implementation. d

Acknowledgments

The authors appreciate the technical support of team members from the FrontEnd Process division at SEMATECH.

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