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The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain

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The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain

Chen Qixing^BS)1'1 and Luo Qiyu(^B^)2

1 Hunan Urban Construction College, Changsha 410015, China 2China National Electronics Import & Export Corp., Beijing 100036, China

Abstract: At present, the architecture of a digital-to-analog converter (DAC) in essence is based on the weight current, and the average value of its D/A signal current increases in geometric series according to its digital signal bits increase, which is 2n-1 times of its least weight current. But for a dual weight resistance chain type DAC, by using the weight voltage manner to D/A conversion, the D/A signal current is fixed to chain current /cha; it is only 1/2n-1 order of magnitude of the average signal current value of the weight current type DAC. Its principle is: n pairs dual weight resistances form a resistance chain, which ensures the constancy of the chain current; if digital signals control the total weight resistance from the output point to the zero potential point, that could directly control the total weight voltage of the output point, so that the digital signals directly turn into a sum of the weight voltage signals; thus the following goals are realized: (1) the total current is less than 200 ^A; (2) the total power consumption is less than 2 mW; (3) an 18-bit conversion can be realized by adopting a multi-grade structure; (4) the chip area is one order of magnitude smaller than the subsection current-steering type DAC; (5) the error depends only on the error of the unit resistance, so it is smaller than the error of the subsection current-steering type DAC; (6) the conversion time is only one action time of switch on or off, so its speed is not lower than the present DAC.

Key words: DAC; weight resistance; dual resistance; resistance chain; weight voltage; weight current DOI: 10.1088/1674-4926/34/3/035010 EEACC: 2520

1. Introduction

This paper puts forward "a weight voltage type DAC based on the dual weight resistance chain", hereafter referred to as the "dual chain DAC"; it is a kind of a DAC that is based on the weighted voltage principle and is completely different from a DAC that is based on the weighted current principle at present, so it will bring large changes in performance characteristics compared to the existing DACs.

At present all of the total current /Z of the DAC is given

^Z — Zsig C ^keep;

where /sig is the D/A signal current, and /keep is the keep current. For the present DAC, the D/A signal current /sig refers to the sum of the weighted currents, and it is a random value; let /unit be the least weight current, the largest value of the /sig be 2n/unit, the average signal current /ave be 2n-1 /unit. The keep current /keep refers to an inner device current which keeps the regular operating state of the DAC (such as the current source, current rudder, and integrated operational amplifiers). For a certain DAC, its keep current /keep is roughly a constant, and it is far less than the average signal current /ave, which is usually not taken into consideration, so the total current /Z is approximately the signal average current /ave.

There are quite a lot of structures for a DAC^1'2], because of the current source type DAC which has a smaller error, so it has become the mainstream DAC. At present manufacturing, there are: binary weighted current source type, unit cur-

rent source type and subsection current-steering type etc. being manufactured, but no matter what kind of a DAC it is at present, in essence the basic principle is the weighted current method: to put a digital signal into different weight (20,21, 22, 23, • • •) current /unit, and then by superposition and through op-amp conversing to an analog voltage signal. Through qualitative analysis it is known that this principle has several defects: (1) the D/A signal current increases geometrically with its conversion bits n growth, producing a great heat, and making the standby time of the mobile communication device shorten; (2) the mass use of the current source and high power consumption make the chip area large, and the manufacture cost is high; (3) the conversion error control depends on the precision of the current source and some compensating measures, so it is very difficult.

In fact the weight current is only a middle step in the DA conversion, but adopting digital-to-analog conversion based on the weight voltage is a kind of direct conversion, which does not need this middle step. The author once put forward two new DAC principles based on the weight voltage, one is a replacement type DAC^3-5!, and another is a weight resistance free link type DAC^6]. These two methods have a common point with the dual chain DAC: that is to make the D/A signal current no longer equal to the sum of the weight current, but a fixed value "chain current /cha"; /cha is constant and very small. Let /cha = /unit, so /cha is only 1/2n-1 order of magnitude of the signal average current /ave of the weight current type DAC. But the present proposed dual chain DAC^7] is a much simpler architecture and is much easier to manufacture; compared

f Corresponding author. Email: chenqixingas@126.com Received 6 August 2012, revised manuscript received 19 October 2012

© 2013 Chinese Institute of Electronics

Fig. 1. Weight voltage type DAC idea diagram.

with the weight current type DAC, it should have more advantages.

2. The basic principle of the dual chain DAC

First look at a conception (Fig. 1): a device consists of a pair of complementary variable resistor Ry and Ry in series; Ry is connected in between the output potential point VY and zero potential point, and Ry is connected in between the power source potential point VP and output potential point VY. When Ry gets larger, Ry gets the same amount smaller, and vice versa. Thus Ry C Ry is a constant value, so the current Icha = VP/(Ry C Ry) is also a constant value, which makes the output voltage VY proportional to the resistance Ry. If Ry is replaced by a group of weight resistance which is controlled by digital signals, then the weight resistance forms a weight voltage, then this device becomes a weight resistance voltage type DAC.

Figure 2 is the principle diagram of the dual chain DAC. Since this is a brand-new principle for a DAC, it is necessary to give some definitions and explanations of concepts before explaining and analyzing it.

(1) Here concepts of apparent resistance, connected resistance and eliminate resistance are put forward, the apparent resistance = connected resistance C eliminate resistance.

(2) The master apparent resistance chain consists of n pieces of master weight resistance 2j R (j = 0, 1, • • •, n - 1) in series, which is connected in between the output potential point VY and the zero potential point; here j is called the weight value. In the same way, the slave apparent resistance chain consists of n pieces of slave weight resistance 2j R0 in series, (plus a unit resistance R, see Fig. 2), which is connected in between the power source potential point VP and the output potential point VY. The master and slave apparent resistance chain (and the unit resistance R) are combined together in series as a total dual apparent resistance chain, among it the master and the slave weight resistance with the same weight value j called the dual resistance.

(3) Each weight resistance is connected in parallel with a switch d, 2j R is in parallel with dj, 2j R0 is in parallel with d j; dj and dj are called as reverse-switches .Therefore it is always that when one of the switches among the reverse-switches

Fig. 2. The dual chain DAC principle diagram.

is switched on, the other inevitably is switched off. Switch dj is connected with corresponding digital signal Dj, the weight value j of the digital signal Dj and switch dj is the same weighted value with the weight value j of weight resistance 2j R.

(4) The weight resistance controlled relationship is: when digital signal Dj = 1, the switch dj which is in parallel with master weight resistance 2j R is switched off, but switch dj which is in parallel with slave weight resistance 2j R0 is switched on; when Dj = 0, dj is switched on; and dj is switched off;

(5) When Dj = 0, 2j R is in short-circuit, which means 2j R disappears from the master resistance chain, which is called "eliminate"; this resistance becomes the ineffective resistance, and it is called the "eliminate resistance" ; when Dj = 1, 2j R is normally linked into the master resistance chain,

which is called "connected", this resistance becomes the effective resistance, and it is called the "connected resistance".

(6) In the master resistance chain, the sum of the eliminated resistance and the connected resistance is called the apparent master weight resistance, therein only the connected weight resistance is the effective resistance, naming the sum of connected weight resistance in the master chain as the master chain weight resistance Ry. In the same way, Ry is named as the slave chain weight resistance. The total chain resistance is Rz = Ry C Ry.

According to the above definitions, the dual chain DAC is constructed; several significant targets like a micro-current, small power consumption, high resolution, small error, small chip area and so on are put forward, now they will be analyzed one by one.

Goal 1: achieving DA conversion of a micro-current and small power consumption. _

Achieving principle: Because d, and d, are switches in reverse with each other, it is always that when one resistance among the dual resistance (2j R and 2j R') is connected and the other inevitably is eliminated, the total chain resistance RZ is constant, namely

Rz = Ry C Ry C R

= (2n-1R C 2n_2R C-----h 21R C 20R C R)

= Fixed value. (2)

Here we have added an R, for the purpose of adjusting RZ from (2n-1)R to 2n R, meaning the VP zero potential is divided into equal sections of 2n. So the chain current

/cha = Vp/Rz = Vp/(2" R). (3)

Known from Eqs. (2) and (3), the chain current /cha is a fixed value.

As the output signal is a voltage, when adopting a voltage follower G in the point of output, G could improve the load ability and could make the extract current from the output point zero, so the chain current /cha could remain constant even it is a micro-current, making the output voltage VY proportional to the master chain resistance value Ry. In the same way, as shown in Fig. 3, each signal output point adopts the voltage follower G, which can be used for ensuring the stability of the signal voltage.

Notice that the weight resistance 2j R is controlled by D,, known from Fig. 2, that the master chain weight resistance Ry is controlled and proportional to the digital signals (D„_1D„_2^ • •D1D0), namely the master chain weight voltage VY is controlled and proportional to the digital signals, so that the weight voltage type DA conversion is achieved. Its output value VY is a quantified voltage, VY forms 2n quantization points, the sequenced quantization points are listed as [0, 1, 2, 3, • • •, 2n - 1]R/Cha (but 2"R/Cha = Vp, it does not belong to the quantization point), and the quantitative interval is R/cha, to rewrite Eq. (3):

R/cha = Vp/2n. (4)

The biggest quantization point is

(2n - 1)R/cha = Vp(2n - 1)/2n. (5)

A DA conversion process is used to describe the work principle. For example, let n = 8, the digital signal is (D7D6D5D4D3D2D1D0) = (10011001), among them 7, 4, 3, 0 bits equal to 1, namely these weight resistances 27R, 24R, 23 R, 20R are in state of connection, so

Ry = 27R C 24R C 23R C 20R = 153R. (6)

The output voltage can be obtained

Vy = (27 C 24 C 23 C 20)R/cha = 153R/cha. (7)

Equation (7) shows that digital signals have been directly converted into analog output voltage VY.

Conclusion 1: The dual chain could mean that the chain current is fixed to /cha, with a small power consumption, and the master chain weight voltage is proportional to the digital signals, thus realizing the weight voltage type DA conversion.

It seems to have realized the digital-to-analog conversion from the above idea, but careful analyses show that the results of the above digital-to-analog conversion is built on the ideal condition, that is, based on the assumption that the switch on-resistance is 0, but in the actual situation this on-resistance cannot be neglected, according to the type of different switch, the on-resistances differ from dozens to hundreds Ohm respectively; if they are not dealt with carefully, that will cause a system error of the converting value of digital-to-analog to become too big ; it is a problem that must be analyzed and solved for the practical circuit.

3. The actual working circuit of the dual chain

Goal 2: To get an actual working circuit by eliminating the negative influence of the on-resistance r0. Though this goal is just one of the steps to reduce errors, it is the most important step to reduce the system error.

Achieving principle: for each actual weight resistance 2j Rr which is on the basis of ideal weight resistance 2j R, adds an additional resistance r1 which equals the switch on-resistance r0, to counteract the negative effect of the on-resistance r0. Therefore, the following two changes are carried out based on the basic principle circuit.

The first change: let the actual weight resistance 2j Rr be the sum of the ideal weight resistance 2j R and the additional resistance r1, namely

2j Rr = 2j R C r1. (8)

A tail is especially drawn on the resistance symbols in the circuit diagram, to remind us that this resistance is an actual weight resistance which has an additional resistance. Make r1 = r0 = r, let both of the additional resistance r1 and on-resistance r0 be called the parasitic resistance r, for r is a resistance which is unpopular but cannot be avoided, so we call it the parasitic resistance.

For a actual weight resistance 2j Rr, if it is in state of elimination, then 2j Rr is short-circuited by d,, this node resistance

(a actual weight resistance and the switch in parallel with it are formed a node) is equal to the on-resistance r of switch dj. If switch dj is turned off, 2j Rr is in a state of being connected, the node resistance is 2j Rr = 2j R C r, it is just an ideal weight resistance 2j R more than the state of elimination . Therefore, to the master chain weight resistance Ry, the sum of the parasitic resistance is fixed to nr.

Ry = the sum of the connected actual weight resistance in the master resistance chain = the sum of the connected ideal weight resistance in the master resistance chain C nr.

Still taking digital signals (D7£5D5D4D3D2DiDo) (10011001) for example, we could obtain

27 Rr C 24 Rr C 23 Rr C 20 Rr = 27 R C 24 R

C 23R C 20R C nr,

Vy = RyIcha = (27 C 24 C 23 C 20)R/Cha C nr/cha; (11)

where nr/cha is the total parasitic voltage, shown by Vnr, and VY is the master chain weight voltage, that is the output voltage including the total parasitic voltage.

The second change: on the basis of above to add an analog summation circuit E, then to get rid of Vnr, the net output voltage VY0 is given by

Vyo = VY - Vnr = (27 C 24 C 23 C 20)R/Cha.

So far, the digital-to-analog conversion of the actual circuit is completed. In fact, the total parasitic voltage only makes the output voltage level move up, and it doesn't influence the waveform, so it could be considered in later steps.

Conclusion 2: for each actual weight resistance 2j Rr, on the basis of the ideal weight resistance 2j R, adding an additional resistance r1 which equals to the on-resistance r0 to offset the negative influence of the on-resistance r0, thus to obtain an actual working circuit.

Yet in fact, this circuit can only make a low bit DAC, to achieve a high bit and low error DAC, there are still two big problems: (1) take 18-bit for an example, the span of weight resistance is 218 times. Suppose the switch whose conduction performance is good should be chosen—the on-resistance value is about 50 Q, the least weight resistance ought to be 210 times the on-resistance, suppose the least weight resistance be 100 Q, the largest resistance is as high as 26.2144 MQ, for such a big resistance, to control its absolute error within 100 Q and keeping stable, it is not only that it cannot be integrated within the IC, it is unable to be realized even by using discrete components; (2) the total parasitic resistance value of the master chain might be as high as 18 x 50 Q = 900 Q, far greater than its least weight resistance, although theoretically the influence of the parasitic resistance could be offset, but the parasitic resistance has randomness, it is hard to avoid it causing conversion errors, even if it might submerge several of the smallest weight resistances. So the conversion of the high bit has to be studied further, thus a multi-grade type dual chain DAC might be a good solution.

Fig. 3. Multilevel dual chain.

4. A practical circuit—a multi-grade type dual chain DAC to realize the conversion of a 2 mW 18-bit

Considering the comprehensive performance characteristics, this section puts forward a DAC of 6-bitx3-grade in Fig. 3, namely this 18-bit DAC is composed by 3 grades that each have a sub DAC of 6 bits; it is a practical circuit which consists of the discrete component, its weight resistances all consist of the unit resistance in series, and certainly a 3-bit x 6-grade is also a good choice.

Goal 3: to integrate a 2 mW and 18-bit dual chain DAC into a chip.

Achieving principle: in Fig. 3, to adopt the unity modularity design, making three sub-grades dual chain DAC a, ^, y with the same structure and resistance parameters, 0 is the wildcard of a, ^, y, Ry^ and Ry^ are (the same as Fig. 2) respectively the master and slave resistance chain of the dual chain DAC of grade 0. Bit n of the three grades are all equal to 6, they are all made by the dual weight resistances of 6 pairs: 25 R0, 24 R0, 23 R0, 22 R0, 21 R0, 20 R0 and 25 R^, 24 R^, 23 R^, 22 R^, 21 R^, 20 R^, naming the least weight resistance R^ as the unit resistance R, according to the characteristics of the integrated circuit technique, the resistance been controlled and 1-10 kQ is more reasonable^, so, let the unit resistance R be equal to 10 kQ, and the power supply voltage VP be equal to 10 V, referring to Eq. (4), to get the grade chain currents /y0, which in each grade are all equal to a fixed value.

= VP/26R = 15.625 ^A.

Grade a converts the highest 6-bit (D17 D16 D15 D14 D13 D12) into the master chain voltage Vya of grade a. In the same way, the grade ^ converts the middle 6-bit (D11D10D9 D8 D7D6) into Vy^, while grade y converts the lowest 6-bit

(D5D4D3D2D1D0) into Vy,, then to add Vy„, Vy,g, Vy, by weighted summation, thus we get an analog value VY of an 18-bit DA conversion, known from the principle of digital-to-analog conversion, so the weighted summation relationship achieved should be

Vy = C Vy^/26 C Vy,/212. (14)

In order to realize the above weighted summation relations, specially designed (see the dashed line box indicated in Fig. 3) voltage dividers FY^ and FY,, the voltage divider FY^ is composed of the voltage-dividing resistor and and the voltage divider FY, is composed of the voltage-dividing resistor Ry1 and R,2, since the conversion bit in each grade is n = 6, let = R, = 63 R, so the dividing voltage ratio B of each grade of voltage divider is

B = R*1/(R*1 C R02) = R/(R C 63R) = 1/26 = 1/2".

According to Fig. 3 and the superposition principle the relationship of the voltage Vy', and V^ is given by

V;, = Vy,/26, (16)

Vy'^ = (Vy^ C Vy'y)/26 = (Vy, C Vy,/26)/26. (17)

Then finally we get Eq. (14)

Vy = Vy„ + Vy; = Vy„ C(Vy^ C Vy, /26)/26 = Vy„ C Vy, / 26 C Vy,/212.

According to Fig. 3, to calculate the total power consumption of the device, all parts (and their currents) of this device include: 3 sub-grade dual chain (3/y^), 36 field-effect tube switches (the grid current of the field-effect tube is equal to zero), 2 voltage dividers (2/^), 5 voltage followers (5/G), 1 integrated summator (/e), so, the maximum of the total current /zmax is

/Zmax = 3/y0 C 2/^max C 5/g C /E . (18)

To compare this with Eq. (1), the D/A signal current /sig = 3/y0 C 2/^max, and the keep current /keep = 5/g C /e.

The sub-grade dual chain current /y^ = 15.625 ^A, this was calculated from Eq. (13).

/^max is the maximum current of the voltage divider /^, according to Eqs. (4) and (5), the maximum value V^max of Vy^ is

V0max = Vp(2n - 1)/2" = (2" - 1)R/y0• (19)

According to Eqs. (15) and (19), the maximum current of the voltage divider FY^ is

/^max = V^max/(R01 C R^2) = (2" — 1)R/y0/2"R

= (2" — 1)/y0/2" * /y0• (20)

/G is the keep current of the voltage follower G, and /e is the keep current of the summator X. For the two items of /G and /e, since the value is too small, only ^A order of magnitude, which has been ignored almost in all the circuit analyzing. In

order to keep the integrality of the analysis, assuming 5/G C /e * /y^, we have got

/Zmax = 3/y0 C 2/^max C 5/g C /e * 6/y0 * 93.75 ^A.

The maximum total power consumption PZ of the DAC is

Pzmax = Vp/zmax * 0.94 mW. (22)

The calculation result of the power consumption is less than 1 mW, in order to leave some leeway, we proposed a power consumption index of 2 mW.

Conclusion 3: by adopting a 6-bit x 3-grade dual chain DAC, the largest span of the weight resistances is only 32 times, its total power consumption is less than 2 mW, so it is suitable for producing an 18-bit DAC, known therefore, the DAC is suitable for an integrated chip.

Goal 4: achieving a lower error conversion than the subsection current-steering type DAC.

Achieving principle: there are four factors to achieve a low error conversion. The first is by using the multistage structure, to shrink the span of the weight resistance, increase the ratio of unit resistance to the on-resistance, such as making the unit resistance 10 k^, much greater than the on-resistance 50 il The second is the unitization of the weight resistance, i.e., to make the weight resistance 2j R be composed by 2j units of the unit resistor R in series, the differential voltage resistance R^1 is equal to the one unit resistance R, the differential voltage resistance R^2 is composed of 26-1 units of the unit resistor R in series, although the quantity of the resistances are increased, from the point of view of chip manufacturing, it can effectively reduce the error of resistance and the producing difficulty. The third is that the error has nothing to do with temperature drift, and when the temperature changes, the resistance changes in proportion, so it does not make the voltage of the quantitative point change. The fourth is under the same technical conditions, the error of the resistance is smaller than the error of the current source.

Goal 5: achieving a chip area an order of magnitude smaller than the subsection current-steering type DAC.

Achieving principle: provided by using a structure of unit resistance to compose the weight resistance, according to the structure of the 6-bitx3-grade, it is known that the components list to design an 18-bit dual chain DAC is: number of unit resistances = 3 x 2 x (1C2C4C8C16C32) = 378, number of switches = 3 x 2 x 6 = 36, two voltage dividers (number of unit resistances = 2 x 64 = 128), five voltage followers, one integrated summator.

For comparison, assume that the implementation possibility of technology like a super large weighted current is not considered , we produce an 18-bit current-steering type DAC, using section means of 5C5C4C4, it needs a current source and a switch each of 2 x 25C24C4 = 84, three thermometer decoders, one integrated op-amp adder. Since there are various structures of the current source, according to the precision differences of the selected current source, and we pay attention to the big effect of power onto the chip area, so that the chip area of the current source at a high current section should be very big; it is estimated that the chip area of this DAC should be 5-30 times as much as the chip area of the dual chain DAC.

5. Analysis and summary on the dual chain DAC performance characteristics

Because of the thorough change on its architecture, the performance characteristics of a dual chain DAC relative to the weight current DAC has also had a big change, now a comparison and summary of some of the most important performance characteristics of the dual chain DAC and today's mainstream section current-steering DAC^ are as follows:

(1) Current amount: the current of the dual chain DAC is about 1/2"_1 of the section current-steering DAC. While the current of the dual chain DAC is roughly a constant value, it is in an order of magnitude of 100 ^A, both have a difference of over hundred times.

(2) Resolution: the multi-grade type dual chain DAC is easy to realize for 18-bit or even higher bit resolution.

(3) Error control: by means of multi-grade and resistance unitization, the error control of the dual chain DAC just depends on the error control of the unit resistance; but the key of the error control of the section current-steering DAC is the unit current source, in the same technology conditions, the error of the unit resistance is far less than that of the error of the unit current source.

(4) The chip area: for a DAC with the same resolution, the chip area of the multi-grade type dual chain DAC is far less than the section current-steering DAC of the mainstream product at present.

(5) Conversion rate: a conversion time of the section current-steering DAC includes the time for the current flow change of the current-steering, plus a time of decoding; while

the dual chain DAC needs only a time of action for the switch

to turn on or off.

(6) Other performance characteristics, such as SNR, burr

and so on which are analyzed theoretically will all be improved.

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