Scholarly article on topic 'Analytical modeling and numerical simulation of novel double-gate InGaAs vertical nanowire transistor device for threshold voltage tuning and improved performance'

Analytical modeling and numerical simulation of novel double-gate InGaAs vertical nanowire transistor device for threshold voltage tuning and improved performance Academic research paper on "Materials engineering"

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Abstract of research paper on Materials engineering, author of scientific article — Subha Subramaniam, Sangeeta M. Joshi, R.N. Awale

Abstract This paper proposes a novel cylindrical double gate In0.53Ga0.47As vertical Nanowire n type device, which offers a higher drive current, better channel potential controllability and reduced short channel effects at ultra-short channel length 14nm through numerical simulation approach. An independent inner gate control is used for threshold voltage tuning. Improvement of drive current in the Double-Gate Vertical Nanowire Transistor (DG-VNWT) structure is achieved by growing the In0.53Ga0.47As Nanowire vertically on silicon substrate. Further to reduce the leakage current of the structure, we propose high-k LaAlO3 outer gate stack in integration with Al2O3 passivation layer and WN metal gate for the first time. Variable threshold voltage tuning is also achieved by inner gate control of the proposed device. An analytical model is built for validating threshold voltage dependence on inner gate voltage. Our results of the analytical model are observed to be at par with TCAD simulations. The proposed DG-VNWT device is compatible with silicon and high-k/metal gate CMOS technology with the unique capability of inner and outer gate control, the most promising scalable candidate for low power applications.

Academic research paper on topic "Analytical modeling and numerical simulation of novel double-gate InGaAs vertical nanowire transistor device for threshold voltage tuning and improved performance"

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Full Length Article

Analytical modeling and numerical simulation of novel double-gate InGaAs vertical nanowire transistor device for threshold voltage tuning and improved performance

Subha Subramaniam aÄ*, Sangeeta M. Joshic, R.N. Awalea

a Department of Electronics, Veeramata Jijabai Technological Institute, University ofMumbai, India b Department of Electronics, Shah and Anchor Kutchhi Engineering College, University ofMumbai, India c Department of Electronics, Vidyalankar Institute of Technology, University of Mumbai, India

ARTICLE INFO

Article history: Received 29 April 2016 Revised 13 August 2016 Accepted 23 August 2016 Available online xxxx

Keywords: Vertical nanowire DG-VNWT High-k gate stack Leakage current Analytical model

ABSTRACT

This paper proposes a novel cylindrical double gate Ina53Gaa47As vertical Nanowire n type device, which offers a higher drive current, better channel potential controllability and reduced short channel effects at ultra-short channel length 14 nm through numerical simulation approach. An independent inner gate control is used for threshold voltage tuning. Improvement of drive current in the Double-Gate Vertical Nanowire Transistor (DG-VNWT) structure is achieved by growing the In053Ga047As Nanowire vertically on silicon substrate. Further to reduce the leakage current of the structure, we propose high-k LaAlO3 outer gate stack in integration with Al2O3 passivation layer and WN metal gate for the first time. Variable threshold voltage tuning is also achieved by inner gate control of the proposed device. An analytical model is built for validating threshold voltage dependence on inner gate voltage. Our results of the analytical model are observed to be at par with TCAD simulations. The proposed DG-VNWT device is compatible with silicon and high-k/metal gate CMOS technology with the unique capability of inner and outer gate control, the most promising scalable candidate for low power applications. © 2016 Karabuk University. Publishing services by Elsevier B.V. This is an open access article under the CC

BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4XI/).

1. Introduction

Extending the technology roadmap with planar MOSFET devices below sub-22 nm technology node is becoming difficult due to dominating quantum mechanical effects and short channel effects in ultra-short channel lengths below 22 nm [1]. At or beyond this node, vertical device architecture can bring in new perspectives with regards to increasing device density and improving performance simultaneously. As the semiconductor industry has to grow more number of devices in a limited area, Vertical Nanowire transistors can be the future candidates in building up low power devices and circuits [2]. The Vertical Nanowire FET is a promising device because of its better short channel effect control by improved gate controllability and the high performance ballistic transport [3]. Ill and V compound semiconductors have been

* Corresponding author at: Research Scholar, Department of Electronics, Veeramata Jijabai Technological Institute, University of Mumbai, India and Associate Professor, Department of Electronics, Shah and Anchor Kutchhi Engineering College, University of Mumbai, India.

E-mail address: subha.sakec@gmail.com (S. Subramaniam). Peer review under responsibility of Karabuk University.

explored as alternative channel materials to increase the drive current in scaled MOSFETs. III-V channel materials are currently being considered as enablers for further CMOS improvement in the near future, with ITRS roadmap indicating an introduction around 2019 [4]. Continued device scaling for future technology nodes requires reduction in equivalent oxide thickness (EOT) of gate dielectric material also. Extendibility of the conventional silicon gate structure is challenged due to exponential increase in gate leakage current. As alternatives to Si gate dielectrics, much work has been done on the research of high permittivity materials [5,6]. It is found that by inserting an ultra-thin layer of Al2O3 as an interfacial layer between high-k and silicon surface can significantly improve the device quality and reduce device variations. A typical HKMG stack structure contains a silicon oxide based interfacial layer (IL), a high-k dielectric, followed by a metal gate electrode. This system is equivalent to two capacitors connected in series. In this paper, a Double-Gate In0 53Ga047AsVertical Nanowire Field Effect Transistor (DG-VNWT) n type and p type device architectures have been designed and evaluated using Visual-TCAD-1.7.4 version [7]. III and V semiconductors are well known for their unique suitability for high frequency applications. It possesses high electron mobility and provides high quality interface with gate dielectrics. The novel

http://dx.doi.org/10.1016/j.jestch.2016.08.014

2215-0986/® 2016 Karabuk University. Publishing services by Elsevier B.V.

This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

idea is to improve the controllability of channel potential and threshold voltage using inner gate technology. With decreasing oxide thickness below 1.5 nm in short channel MOSFET causes more leakage current. The obvious remedy is to replace SiO2 with an insulator that has significantly higher dielectric constant than 3.9. This will allow the device to operate using the same capacitance, but with a higher physical thickness that suppresses direct current leakage [8]. Leakage current is the major issue in short channel MOSFETs and in order to reduce the leakage current of the structure a gate stack with LaAlO3 with a thin Al2O3 layer and WN metal gate is proposed. Variable threshold voltage tuning is possible by the inner gate and it provides better Vth control. An analytical model is built for validating threshold voltage dependence on inner gate voltage. The model depicts that the capacitances formed by inner gate, outer gate and Nanowire determines the changes in the threshold voltage with respect to inner gate voltage, which are defined by the device structure and materials.

2. Device structure and simulation framework

We propose a novel double-gate ln0.53Ga0.47AsVertical Nano-wire Transistor structure on silicon [9]. Position controlled growth of single surrounding gate ln0.53Ga0.47As vertical Nanowire transistor is reported experimentally recently. Figs. 1a and 1b shows the 3D schematic structure of the DG-VNWT device considered in the numerical simulation. As shown in Fig. 1a the Nanowire is grown vertically with ln0 53 Gao.47As on silicon. It is covered with High-K Metal Gate (HKMG) stack of Al2O3 + LaAlO3 + WN at the outer gate and Al2O3 + WN gate stack at inner gate. The entire structure is built on silicon and SiO2 is deposited above silicon to prevent leakages and fringing effects. The device transfer and drain characteristics are depicted in Figs. 2a and 2b respectively and the simulation parameters are listed in Table 1. Material properties used in simulation are listed in Table 2. Due to lower hole mobility, variation in threshold voltage, SS and DIBL values p type DG-VNWT drain current is lower than the n type DG-VNWT device.

To investigate the device performance of DG-VNWT, 3D TCAD simulations are performed using Visual TCAD Device Simulator with advanced quantum models.

The partial differential equations solved in the simulations are,

V- eVW = —q(p — n + N)

where W is the electrostatic potential of the vacuum level, e is the material permittivity, q is the electronic charge, n is the electron density, p is the hole density and N is the impurity concentration.

rr , r, dn

V - Jn = q - Rn + q - —

V -Jp = —q - Rp + q - @t

Jn = qin[ —nVv +-Vn

Jp = qip[ —pVv — ^ -Vp

Fig. 1a. 3D isometric view of DG-VNWT structure considered for numerical simulation using Visual TCAD.

Jn p is the carrier current density, Rn, Rp is the net electron-hole pair recombination rate, KB is the Boltzmann's constant.

The Visual TCAD device simulator solves Schrodinger equation along with Poisson equation continuously to achieve self-consistency. Band structure is modeled by including bandgap Eg, effective density of states in the conduction band Nc and valance band Nv and the intrinsic carrier concentration nie. Quantum effects are included in the simulation by adding Schenk's Bandgap narrowing model which includes band gap narrowing [10] and Kane's model which includes Band to Band Tunneling effect [11]. Yeager's model is included in Visual TCAD device simulator to describe high field effect and mobility for ln053Ga047As [12]. The device structure is optimized and designed for 14 nm gate length with loff 1 nA as per ITRS requirements [13]. In the device structure dislocations occur at atomic level between the junctions if the interface strain is too long between layers. This is related to the thickness of the over layer and denoted as critical thickness. A critical thickness of ~0.9 nm for InAs grown on (0 0 1) GaAs, is assumed in the simulation using energy balance approach for ln0.53Ga0.47As. This critical thickness had shown good agreement with experimental findings enabled in molecular beam epitaxy

Vgs Gate Voltage(V)

Fig. 2a. Transfer Characteristics of InGaAs DG-VNWT n and p structure obtained from 3D numerical simulations for Vds-sat at 1 V and Vds-linear for 0.05 V in log scale and inset figure in linear scale.

0.4 0.5 0.6

Vds-drain voltage(v)

Fig. 2b. Output characteristics of InGaAs DG-VNWT for various gate drive voltages, obtained from 3D numerical simulations employing Drift and Diffusion and quantum models by keeping VGi at 0 V.

3. Proposed process flow

The proposed device can be fabricated using top down approach by taking a silicon wafer and growing an In053Ga047As Nanowire using TmGa, TmIn and AsH3 as material sources by flow-rate modulation epitaxy at 670 °C [15]. The height of the Nanowire can be

controlled by Molecular beam Epitaxy up to 100 nm. Plasma etching can be used to make an inner gate opening and Al2O3 can be deposited using atomic layer deposition method [16,17]. Outer gate stack can be formed by depositing Al2O3 and LaAlO3 with Atomic Layer Deposition (ALD) method with self-limited oxidation techniques. Depositing WN at inner and outer gate and the contact

Table 1

Simulation Parameters for DG-VNWT in VisualTCAD.

Symbol Parameter Values for DG-VNWT

Lg Channel Length 14 nm

tox1 Inner gate oxide thickness-Al2O3 1 nm

tlL Outer gate IL layer thickness-Al2O3 0.5 nm

tox2 Outer gate HK layer thickness-LaAlO3 1 nm

HNW Height of Nanowire 100 nm

dNW outer Outer Diameter of Nanowire 150 nm

dNW inner Inner Diameter of Nanowire 50 nm

Wnw Effective Width of Nanowire 50 nm

Nchannel Doping of channel 5 x 1018cm~3

Nsource, Ndrain Doping of Source and Drain 5 x 1018cm~3

Table 2

Material Properties of In0.53Ga0.47As.

Symbol Parameter In0.53Ga0.47As

ao(A°) Lattice Constant 5.869

Eg(eV) Band Gap 0.75

1e(cm2/vs) Electron Mobility 7000

1h(cm2/vs) Hole Mobility 300

D-n(cm2/s) Diffusivity-n 300

D-p(cm2/s) Diffusivity-p 7.5

P(gm/cm3) Density 5.5

can be made by Rapid Thermal Annealing method [18]. The entire structure can be annealed at 420 °C in N2 to obtain ohmic contact at source and drain regions as illustrated in Fig. 3. New lithograph-ical techniques like Nano imprint and electron beam lithography and Nanosphere lithography [19] can be followed to fabricate DG-VNWT at these ultra-scale dimensions. The three dimensional

DG-VNWT architecture could further increase the transistor density through the additional ability to integrate multiple gate geometry.

4. Simulation results and discussions

Width optimization work is carried out for DG-VNWT device for various Nanowire widths ranging from 80 nm to 10 nm [20]. Width of DG-VNWT is the difference between r2 and r1 i.e. (r2 - r1), where r1 is the inner gate radius and r2 is the outer gate radius of DG-VNWT. Ioff is kept constant as 1 nA in simulation conditions. Ion, SS, DIBL values are observed and plotted for various Nanowire effective widths. As shown in Figs. 4 and 5, DG-VNWT with 50 nm width provides a good short channel control and high Ion current. For greater width WNW > 50 nm On-current decreases, due to higher threshold voltage at the edges of DG-VNWT [21]. The reason is in larger diameters fringing capacitances increases due to the leakage of electric field in the edges of cylindrical shaped vertical nanowire transistors. Due to increase in fringing capacitance threshold voltage increases. Major increase in On-current is controlled in ultra-small diameters of DG-VNWT structure due to the increase in quantum mechanical effects. However, minor increase in On-current is observed in Fig. 4 for WNW < 50 -nm. As minor variations are only observed in SS, DIBL and Ion below 50 nm, effective width of DG-VNWT is optimized at 50 nm. Fabrication of DG-VNWT below 50 nm width may become difficult, as the inner gate should be fabricated inside the vertical Nanowire structure.

The vertical Nanowire FET structure with cylindrical doublegate geometry gives better electrostatic control with a high on current up to 7.74 mA. The significant figure of merit for transistor

• Silicon Wafer <100> orientation

• Thermal oxidation for SiO2growth at 900°C

• Circular opening with 150nm diameter by Electron Beam Lithography and wet chemical etching

• Ino.53Gao.47As Nanowire formation at 670°C using Metal Organic Vapour Phase Epitaxy

• Inner gate opening with 50nm by Electron beam lithography and wet chemical etching

• Deposition of Al2O3in 50nm opening using atomic layer deposition method inside the Nanowire

• Epitaxy and in-situ doped source/drain

• Electron beam lithography and deposition of Al2O3 of 1nm using atomic layer deposition and formation of inner oxide

• Electron beam lithography and deposition of WN metal inner gate formation using radio frequency sputtering technique

• Al2O3 high-k material deposition by Atomic Layer Deposition with A thickness of 10nm at EOT=1.86nm for outer gate

• Gate material WN using Radio Frequency Sputtering technique for outer gate formation

• Nanowire spin coating with benzocyclobutane (BCB)

• Etching of gate oxide Al2O3 by reactive-ion etching (RIE).

• Spin coating with BCB and reactive-ion etching to isolate the gate and drain metals.

• A multilayer of Ni/Al evaporation onto lithographically defined region to serve as drain contact

• A multilayer of Ni/Al evaporation onto lithographically defined region to serve as source contact

• Annealing at 420°C in N2 to obtain ohmic contacts at source and drain regions

Fig. 3. Key steps of process flow for the In053Ga047As VNWT on silicon substrate.

60 0.4 r-1-1-1-

0.35 -> 0.3 -

30 40 50

Width of Nanowire(nm)

Fig. 4. Width optimization of DG-VNWT at 14 nm gate length with SS and DIBL at Vds at 1 V, Vg1 at 0 V and Vg2 at 1 V.

-0.2 0 0.2 0.4 0.6 0.8 1 1.2

Voltage at inner gate-Vgl(V)

Fig. 6. Tuning of threshold voltage Vth with inner gate voltage Vg1 for In0 53Ga047As DG-VNWT (Outer gate voltage Vg2 kept at 1 V).

8 7.8 7.6

7.4 § 7.2

O 6.8 6.6 6.4 6.2

30 40 50

Width of Nanowire(nm)

Fig. 5. Width optimization of DG-VNWT at 14 nm gate length with Ion at Vds at 1 V, Vg1 at 0 V and Vg2 at 1 V.

performance includes the transconductance (gm), on-off current ratio, subthreshold slope (SS) and Drain Induced Barrier Lowering (DIBL). The Ion/Ioff ratio is the ratio of Ids at current saturation Ion to Ids at depletion.

The gm of the device is 8.2uS for Vg1 at 0 V and Vg2 at 1 V and is suitable for low power and RF applications. Fig. 6 depicts the variable Vth tuning curve with different Vg1 control for DG-VNWT. By applying different voltages to the inner gate Vg1, variable Vth can be obtained using the device. A variable threshold voltage configuration leads to high speed gate drive and ultra-low power applications. The extrapolation method is used to extract threshold voltage in the linear region [22] and the constant current method is used in saturation region for higher drain voltages.

Further reduction in SS and leakage current can be obtained by the integration of high-k gate stack in DG-VNWT structure. The DG-VNWT structure provides SS of 62 mV/decade and DIBL of 32 mV/V due to good coupling of both the gates. Fig. 7 depicts the variation in On-current and Transconductance with various inner gate voltages at Vg2 at 1 V. On-Current and Transconductance both increases with increase in inner gate voltage, due to the better electrostatic control provided by both the gates in DG-VNWT structure.

An apparent way to scale EOT of high k material is to reduce physical thickness of the high-k layer and which leads to charge

0.3 0.4 0.5 0.6 0.7 Voltage at inner gate-Vgl(v)

Fig. 7. Variation in On-Current and Transconductance with inner gate voltage Vgi for In053Ga047As DG-VNWT (Outer gate voltage Vg2 kept at 1 V).

trapping with processing. To avoid charge trapping in In0 53Ga047-As Nanowires a small Interface Layer [IL] of Al2O3 is introduced in HKMG stack. This enables conventional Al2O3 as a dielectric layer and avoids charge trapping. Instead of increasing the k value of IL layer, we propose to reduce the physical thickness of IL layer up to 0.5 nm. The value of EOTHK is calculated using the following formula.

m-r KSiO2

EOTnk = --1

K high-k

high-k

Fig. 8 shows the EOT optimization curve for DG-VNWT with high-k LaAlO3 + Al2O3 + WN at outer gate stack and Al2O3 + WN at inner gate stack. Physical thickness of Al2O3 at outer gate is kept constant as 0.5 nm and the inner gate EOT of Al2O3 is kept at 1 nm [23,24]. The simulations are performed for various values of EOT of LaAlO3 from 0.3 nm to 1 nm to optimize the values of equivalent oxide thickness of high-k LaAlO3.

DG-VNWT at 14 nm gate length with Al2O3 + LaAlO3 + WN gate stack at outer gate and Al2O3 + WN at inner gate is simulated and proposed as a model gate stack system for the better performance. A better Vth control is achieved by this proposed gate stack by obtaining a Vth of 0.35 V. EOT of the proposed high-k material LaAlO3 is optimized to 0.68 nm to maintain the tradeoff between Ion and Ioff as shown in Fig. 8.

Fig. 8. EOT optimization curve of DG-VNWT with various values of EOT and Ion, Ioff for LaAlO3 in outer gate stack with IL of AL2O3 with a thickness of 0.5 nm and keeping inner gate oxide with Al2O3 at 1 nm and inset shows EOT vs Ion/Ioff.

5. Device analytical model

In this section an analytical threshold voltage model is developed for the proposed DG-VNWT with cylindrical all around outer gate and inner gate. DG-VNWT provides greater electrostatic control and by varying the inner gate voltage the threshold voltage of the device can be tuned. However, the analytical model developed can be used to design the device for variable threshold voltage depends on the application. Variable threshold voltage tuning can lead to design of low power circuits [25,26].

The proposed DG-VNWT with independent outer gate and inner gate can be modeled based on the Silicon Nanowire Transistor model as follows [27]. Total charges at the outer gate and inner gate are equated by the following equation as,

Q1 = Q 2

where Qj the total is charge of inner gate and Q2 is the total charge of outer gate in DG-VNWT. The inner gate radius is denoted as r1, inner gate capacitance as Ci and outer gate radius is denoted as r2, outer gate capacitance as C2. So

Va C1 = VC2C2 (8)

The inner gate capacitance C1 is equal to the inner gate oxide capacitance Cox1. The outer gate total capacitance C2 is expressed as the series capacitances of the Nanowire capacitance (CNW) and the outer gate oxide capacitance (Cox2) [9].

C1 = Cox1

C2 Cnw Cox2

Cox2 Cn

(CNW + Cox2)

Substituting C1 and C2 in Eq. (8),

AVctCox1(Cnw + Cox2) = DVg2CnwCox2

(9) (10)

(11) (12)

AV« = AVC:

CnwCo:

Cox1 (Cnw + cox2)

CNWCo;

DVG2 Cox1 (CNW + Cox2)

where,

Cox1 = capacitance between Gate1 and Nanowire, Cox2 = capacitance between Nanowire and Gate2, CNW=Capacitance of Nanowire.

The proposed DG-VNWT structure has an outer gate stack with Al2O3 + LaAlO3 + WN and inner gate stack with Al2O3 + WN.tIL indicates the outer gate oxide Al2O3 with 0.5 nm as a passivation layer for depositing high-k tox1 with 1 nm. The passivation layer reduces interface traps and works well with In0.53Ga0.47As to reduce the semiconductor/oxide interface states. For the inner gate Al2O3 is kept at 1 nm thickness and denoted as tox2. eInGaAS is taken as 14.1 in this model system and numerical simulations. k is denoted as the dielectric constant of the high-k material.

£o£ox(r2 — r1)Lg

£o£ox(r2 — r1)Lg

Considering the cylindrical structure of Vertical Nanowire, the Nanowire capacitance can be expressed as cylindrical capacitance Cnw by Eq. (17).

Cnw —

'InGaAsLNW

The proposed DG-VNWT can be surrounded with oxide to prevent fringing effects in Nanowires when grown in arrays [28]. Vertical dummy nanowires can also be grown with conducting

Table 3

Comparisons of calculations based on our analytical model and visualtcad simulations for DG-VNWT with different gate dielectric constant k with outer gate LaAlO3 EOT = 0.68 nm, outer gate IL layer of Al2O3 0.5 nm and inner gate Al2O31 nm.

k = 3.9 K = 9 k = 22 k = 25 K = 50 K = 60

SiO2 Al2O3 HfO2 LaAlO3 TiO2 HfTiO4

Vt/Vg2 of our analytical model 0.119 0.141 0.154 0.155 0.159 0.160

Vt/Vg2 obtained through Visual TCAD simulation 0.098 0.118 0.124 0.128 0.137 0.141

Relative Difference in Vt/Vg2 17.6% 16.3% 19.4% 17.4% 13.8% 11.8%

Nanowires in order to nullify the fringing effects in batch fabrication of vertical Nanowires [29]. So, fringing capacitances of the Vertical Nanowire is neglected in this analytical model. Substituting Eq. (14) and solving for jVj we get,

DVt 2p [fox1 'f + tjL jx] EoEInGaAsLNW'n(if) (tox2 'f)

DVg2 (tox2 ^f) ln^^P (tox2 e?) £o ernCaAsLNW + 'o Eoxfc - ^ln^) Lnw]

DVt _ 2p [tox1 f + tIL Sfj EinGaAs (19)

DVg2 [2P [tox2 ^ EinGaAs + Eoxfc - r1 )ln ]

Eq. (19) deduces that the change in Vth in DG-VNWT at different inner gate voltages can be determined by the capacitance between inner and outer gate, inner diameter and outer diameter which are defined by the device structures and materials. Numerical simulations are carried out by keeping inner gate oxide as Al2O3 with thickness of 1 nm and tIL also as Al2O3 with 0.5 nm.

The high-k material of outer gate is varied and result based on our analytical model is compared with Visual TCAD simulations. The corresponding relative difference is also shown in Table 3. Mostly in all cases, it is shown that our analytical model agrees well and the model is at par with the simulation data.

6. Conclusion

We have demonstrated a novel DG-VNWT with In0.53Ga0.47 As on silicon along with inner and outer gates for variable threshold voltage tuning and better electrostatic control. An analytical model is built for validating threshold voltage dependence on inner gate voltage. The model depicts that the capacitances formed by inner gate, outer gate and Nanowire determines the changes in the threshold voltage with respect to inner gate voltage. The analytical model results are at par with TCAD simulation results. The relative difference between TCAD simulation and the analytical model is 11.8% at k value of 60 which shows a close match of the model. The device is compatible with the latest state of art gate HKMG CMOS technology with the unique capability of independent inner gate control for DG-VNWT at 14 nm gate length and suitable for low power applications.

Acknowledgment

We express our sincere thanks to Mr. Amit Saini, Cadre Design for his valuable technical support.

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