Scholarly article on topic 'Design and implementation of a low-power hybrid capacitive MEMS oscillator'

Design and implementation of a low-power hybrid capacitive MEMS oscillator Academic research paper on "Electrical engineering, electronic engineering, information engineering"

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Abstract of research paper on Electrical engineering, electronic engineering, information engineering, author of scientific article — Cuong Do, Andreja Erbes, Jize Yan, Ashwin A. Seshia

Abstract This paper reports on the design and implementation of a low power MEMS oscillator based on capacitively transduced silicon micromachined resonators. The analysis shows how design parameters of MEMS resonator impact on the power requirement of the oscillator, particularly with a view towards informing the impact of device and interface parasitics. The analysis is based on resonators fabricated in a 2-μm gap SOI-MEMS foundry process. The sustaining circuit, which is based on a Pierce topology, is fabricated in a standard 0.35μm process. An automatic gain control (AGC) is adopted to suppress the mechanical non-linearity so as to improve oscillator frequency stability. The 110-kHz MEMS and CMOS dies are assembled within a standard ceramic package and electrically integrated through wire bonds. The oscillator core consumes 400nA (900nA with parasitic readout loading) at 1.2-V dc supply while demonstrating a frequency stability of less than 0.5ppm. The work provides a thorough analysis and design guidelines for both MEMS and CMOS circuit design with a view towards minimizing overall power consumption. The implications of the results reported in this paper are towards enabling a new class of low power resonant MEMS sensors that utilize the oscillator as a front-end building block.

Academic research paper on topic "Design and implementation of a low-power hybrid capacitive MEMS oscillator"

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Design and implementation of a low-power hybrid capacitive MEMS oscillator

Cuong Do *, Andreja Erbes, Jize Yan, Ashwin A. Seshia

Department of Engineering, University of Cambridge, Cambridge, United Kingdom


This paper reports on the design and implementation of a low power MEMS oscillator based on capa-citively transduced silicon micromachined resonators. The analysis shows how design parameters of MEMS resonator impact on the power requirement of the oscillator, particularly with a view towards informing the impact of device and interface parasitics. The analysis is based on resonators fabricated in a 2-pm gap SOI-MEMS foundry process. The sustaining circuit, which is based on a Pierce topology, is fabricated in a standard 0.35 pm process. An automatic gain control (AGC) is adopted to suppress the mechanical non-linearity so as to improve oscillator frequency stability. The 110-kHz MEMS and CMOS dies are assembled within a standard ceramic package and electrically integrated through wire bonds. The oscillator core consumes 400 nA (900 nA with parasitic readout loading) at 1.2-V dc supply while demonstrating a frequency stability of less than 0.5 ppm. The work provides a thorough analysis and design guidelines for both MEMS and CMOS circuit design with a view towards minimizing overall power consumption. The implications of the results reported in this paper are towards enabling a new class of low power resonant MEMS sensors that utilize the oscillator as a front-end building block.

© 2016 The Authors. Published by Elsevier Ltd. All rights reserved.


Article history: Received 10 December 2015 Received in revised form 27 May 2016 Accepted 13 July 2016

Keywords: MEMS

Low-power oscillators Sensor interface circuits Pierce topology Amplitude limiting control

1. Introduction

Micromachined resonant sensors have been researched for several decades due to the advantages inherent in chip-scale integration and dimensional scaling [1]. Semiconductor batch fabrication enables system integration and significantly reduced costs as compared to traditional resonant sensors. Recent technology breakthroughs in the areas of wafer-level vacuum packaging and passive temperature correction applied to MEMS-based timing and frequency references have addressed two of the significant technical challenges limiting translation to a potentially wide range of device applications including the measurement of acceleration [2,3], strain [4] and rotation rate [5,6]. Central to the design of these devices is a micromechanical oscillator [7] whose physical parameters are functions of the measurands of interest. The mi-cromechanical oscillator typically embeds the resonator in the feedback loop of a sustaining amplifier and a variety of circuit topologies may be employed for this purpose.

The minimization of power dissipation in sensors is of increasing interest in various applications such as consumer products and distributed wireless sensor nodes for environmental and infrastructure monitoring [8]. One of the under-stated advantages of resonant sensors is the potential for significantly reduced power

* Corresponding author.

0026-2692/© 2016 The Authors. Published by Elsevier Ltd. All rights reserved.

dissipation has not been comprehensively addressed in previous studies [7,9,10]. The capacitive MEMS oscillator based on a Pierce topology [11] previously implemented for real-time clocks utilizing MEMS resonators [12,13] with low-power consumption were demonstrated, though detailed design analysis was not provided. This paper reports on the comprehensive analysis and implementation of an oscillator circuit in standard CMOS as a low power front-end circuit interface for micromachined resonant sensors that addresses the power minimization criterion. The detailed analysis would help both the MEMS and circuit engineers to design a power-optimized capacitive MEMS oscillator based on the availability of the process.

The circuit is designed and fabricated in a 0.35 ^m foundry CMOS technology and integrated together in a hybrid two-chip format together with a 110 kHz electro-statically actuated micro-machined single-crystal silicon double-ended tuning fork (DETF) resonator. Double-ended tuning fork resonators operating in this frequency range have been previously integrated into a variety of device applications addressed above, and therefore the results reported in this paper potentially have wide device applicability. The CMOS read-out circuit is specifically designed with no additional bias control requirement apart from the supply voltage provided that can vary over a wide range from 1.1 V to 3.3 V.

The remainder of the paper is organized as follows: Section 2 describes the DETF device structure and its equivalent electrical model. Section 3 presents the oscillator design based on the

developed model with a focus on low-power design considerations. Experimental results are presented in Section 4. Finally, conclusions and future extensions of this research are discussed in Section 5.

2. Resonator model

An optical micrograph of the DETF resonator used in this work is shown in Fig. 1(a). The device is designed and fabricated in a commercial foundry process using a silicon-on-insulator (SOI) MEMS process through MEMSCAP Inc., USA. The operating principle of DETF resonator has been discussed in previous papers [2,14,15].

The thickness of the SOI layer is t=25 ^m. A schematic of the device outlining critical dimensions and device features is shown in Fig. 1(b). The dimensions of the tines are w=5 ^m, L=420 ^m and the two tines are separated by a gap of 8 ^m. The dimensions of the attached electrodes are wa = 10 ^m, La=300 ^m. This resonator is capacitively actuated and sensed using a nominal designed gap (g=2 ^m).

The Quality factor, Q, of the system is dependent on the damping coefficient, y, of the resonator in a given operating environment. The fundamental mode resonant frequency is estimated by the expression [2].


where E and p are Young modulus and density of the resonator material, which is silicon in this work, other parameters can be found in Fig. 1(b).

Capacitive driving and sensing is utilized for the resonator in this work. To bias and excite the resonator, a dc-bias voltage, Vbias, is applied to the body of the device, while an ac, vac, voltage applied to the driving electrode, where generally, Vbias» vac. This voltage combination (Vbias+vac) generates a time-varying force that drives the beam into mechanical vibration. The electrostatic force is obtained from

Fe (X, t) = 1 (Vbias + Vac (t))2dC 2 dX

■■ 1 (Vgias + 2 Vbias Vac (t) + Va2c (t))2dC 2 dX

where C is a capacitance between the driving and beam electrodes:

C (X) :

where e0 is the permittivity of free space, A is the electrode area (A = La t), g is the actuation gap, and x is the deflection of the moving electrode.

The electrostatic force in (2) consists of three frequency components: a dc-force due to term Vb2ias, a force at the excitation frequency due to the cross term 2Vbias vac (t), and a force at twice the excitation frequency due to square-term v2c (t). Assuming the deflection is very small compared to the actuation gap x « g and the forcing term at the excitation frequency dominates, we get

Fe (t) = Vbi,

s 2 g2

Vac (t)

The time-varying capacitance between the beam and the electrodes through which a motional current is

i = -(Vbia = - (Vbias

■ Vac )

e0A dX (g - X)2 d

)dC dX

c) dX dt £0A dX g2 dt

with Vbias » Vac and x « g,

The ac current through the capacitor in (5) is termed as the motional current. The minus sign on the right hand side denotes that the beam motional current flows in reverse with the applied ac signal input. As be seen on both (4) and (5), a new variable can be defined, termed the electromechanical transduction factor [16],

n = Vbias, for the time-varying capacitance of the system.

As the DETF resonator is symmetric, the electrostatic force and the motional output on the sensing pad (in-plane mode) are

Fe (t)

i (t ) = n

nVac (t) dX dt

The amplitude of vibration is highest at the resonance frequency where frequency of vac is coincident with the beam resonant frequency f0. The forced vibration of the resonator shown in Fig.1(c) can be described as

Fig. 1. (a) Micrograph of the fabricated silicon DETF resonator. (b) Critical features of the MEMS device. (c) Spring-mass-damper equivalent of the MEMS resonator with electrostatic transduction.

d2X dX , „ _

meff—^ + T— + keff X = Fe (t)

at2 at

Substituting Fe(t) and — in (6) into (7) gives

meff di t ■ keff r..^

-^f— + l +--eï1 / t = Vac (t)

n dt n n J

The behavior of motional current to ac actuation voltage in (8) is similarly found in a series RLC-circuit with equivalent parameters for motional resistance, motional inductance and motional capacitance as

Rm = —2 =

. meff

•Jkeff meff _ Vkeffmeff g4

Q vg^sc^2

Cm = ■

The spring-mass equivalent system in (7) of the beam resonator can now be represented by the electrical equivalent circuit as

Lm — + Rm i + -1 /idt = Vac (t)

The motional elements are governed by the stiffness and mass of the resonator, the electromechanical transduction factor and the damping factor of the resonator. This electrical model is an essential input to oscillator circuit design, presented in the next section. Additionally, the feed-through parasitic capacitor Cf that directly couples the drive and sense ports can be extracted through measurements. Proper grounding is required to reduce the feed-through coupling. Note that Cf is the feedthrough capacitance between drive and sense electrodes while Cd and Cs are parasitic capacitances associated with the drive and sense pads

respectively. Furthermore, the designed nominal parameters are not very well-controlled during the fabrication process, especially the actuation gap, and therefore electrical parameters are generally extracted by the measured system response.

Fig. 2(a) shows the measured transmission response of the resonator at Vbias = 10 V under vacuum conditions. The quality factor (Q) of the resonator is seen to be 32,000 at 30 mTorr pressure and motion resistance Rm = 1.1 M^. This translates to an actual effective electrical gap of about 3.1 ^m, which is much larger than that for the nominal design. The value of Rm also increases considerably as Vbias decreases.

The extracted linear model parameters from measurement Vbias = 10 V, P=30 mTorr are shown in Table 1. The values of Cd and Cs are estimated based on the pad sizes and process parameters provided. The device parameters are normally functions of the bias voltage and environmental conditions including pressure and temperature [16]. Fig. 3 shows a simulation figure of quality factor, Q, and motion resistance, Rm, versus temperature based on (1) and (9) with some estimated values found in [17,18]. It is predicted that the motion resistance could be changed from more than two times when temperature varies from - 10°C to 80 °C. Therefore, at different temperature, the model parameters in Table 1 should be updated accordingly.

3. Oscillator design

3.1. Pierce topology

A feedback oscillator is constructed by connecting the resonator to a sustaining amplifier as shown in Fig. 4(a). The two conditions that must be satisfied for sustaining oscillation include, (i) the loop gain should be higher than or equal to unity, (ii) the phase shift around the loop must be zero (or a multiple of 360°) [11,16,19]. A Pierce topology is employed due to its simplicity,

Fig. 2. (a) Measured admittance plot of the DETF resonator. (b) Equivalent electrical circuit model.

Table 1

Equivalent circuit model parameters of the mems resonator at room temperature (25 °C), Vbias = 10 V, P= 30mTorr.

Model parameters Value Unit

Rm 1.1 Mn

Lm 52,200 H

Cm 41.7 aF

Cf 200 fF

Q 32,000

fo 107,85 kHz

Cd, Cf 1 PF

5 xlO4 2

i i i i i

4.5 1.8

4 ./Of 1.6

3.5 <y 3 s-------— 1.4 a 12 S

2.5 ___________ 1 5

2 -________ 0.8

1.5 Room temp 0.6

-'lO 0 10 20 30 40 50 60 70 80" Temperature [°C]

Fig. 3. Simulation figure of Q and Rm versus temperature. Assuming TCQ=3 [17] and TCE = -60 ppm/°C [18] and neglecting other temperature variant factors.

Fig. 4. (a) Schematic of the bonding diagram between CMOS die and MEMS die. (b) Simplified block diagram of oscillator.

the linear model is sufficient to evaluate the parameters to satisfy the critical condition for oscillation. A single MOS transistor can be employed to provide the required transconductance to form a three-point oscillator. A comprehensive and detailed analysis of the three-point oscillator can be found in the work of Vittoz [11].

In a two-die MEMS-CMOS oscillator as in this work, the total value of the capacitor Cp includes all parasitic and stray capacitances on both dies and is estimated to be approximately 2 pF in this work. The critical transconductance required to sustain steady oscillation is

2 (Cp2 + 2Cf Cp )2

The parasitic capacitance Cp is unavoidable, and is particularly of concern when considering a hybrid integration of the MEMS and CMOS die. Fortuitously the Pierce configuration requires capacitive loading at the input and output nodes of the resonator/ amplifier to form a three-point oscillator [11]. However, a large value of Cp will require large gm,crit and, consequently, large static power is dissipated. Therefore, Cp should be considered carefully so as to minimize power while satisfying Pierce oscillator criteria. The effective oscillation frequency output, which is lightly larger than the resonant frequency - frequency pulling-, also depends on Cp as

/out fm fm

(Cf + CP )

Good frequency stability requires small Af, and hence a large value of Cp is preferred, but at the cost of increasing power consumption. This design dilemma is the classic trade-off between power consumption and stability for the oscillator.

The maximum negative resistance provided by the circuit when the value of transconductance gm reaches the optimum value of gmopt can be found as


2C + -p 2Cp + Cf

Pierce oscillator must be larger than motional resistance of the resonator to allow oscillation. The following condition needs to be satisfied with sufficiently large margin.

> 21 1 + Cf-

Based on the estimated model parameters, the complex plane representation of the three-point oscillator [11] for the above system is shown in Fig. 5. It is shown that at Vbias = 10 V, the required value of gm for the device parameters considered in this work is in the range (A to B) from 2.91 mS to 87.8 mS to meet the conditions for oscillation startup.

However, as the actual value of Cp is unknown, particularly with uncertainties due to the hybrid integration of MEMS and CMOS, it is desirable to evaluate the full range of the working region for gm as shown in Fig. 6. If Cp is estimated to be around 13 pF, gm should be designed within the range from 6-21 ^S to guarantee oscillation startup.

The maximum negative resistance, Rmmax provided by the

stability and potential for power minimization with gain provided by a single transistor [11,13].

The equivalent circuit representation of the resonator described here is only accurate in the linear region and must be appropriately modified when the resonator is driven into a non-linear regime [14]. However, at start-up, when the amplitude is small,

3.2. Power analysis and design consideration

By comparing parameters in (11), it is easy to spot that the dominating parameter that sets the power requirement is the operation frequency as it directly proportional to ®02. Therefore, scaling to high frequencies results in higher power consumption.

Fig. 5. Complex plane analysis of the oscillator follows the analysis of a three-point oscillator for the extracted parameters in Table 1.


6 -»-198 ^iS

1-»21 (iS Working region for gm design

Fig. 6. Working region for gm with Cp is estimated in a range of 1 to 3 pF.

As motion resistance, Rm, is increased with temperature, Fig. 3, higher power is required at higher temperature condition.

In Fig. 7, the critical transconductance, gm,crit, and frequency

i?m= 1.1 MQ Cf = 200 fF f0= 107.85 kHz

Fig. 7. gm,crit and A///m versus Cp.

100 200 300 400 500 Feed-through capacitance, Cf [fF]

Fig. 8. gm,crit versus Cf with different Cp.

pulling are plotted as functions of Cp with all other parameters kept fixed as in Table 1. It is seen that power dissipation can be reduced if the value of Cp decreases, but not lower than 0.5 pF, where the start-up criteria not met. Therefore, in the monolithic integration of MEMS and CMOS [20], Cp can be minimized even further to reduce the power consumption. However, Cp should be big enough to satisfy the condition (14) with sufficient margin.

The feed-through capacitance, Cf, is another crucial parameter that should be taken into account. There is a relationship between Cf and Cp that needs to be considered to ensure oscillator start up. For different values of Cp, the working range of Cf can be changed accordingly as shown in Fig. 8. The bigger the value of feed-through capacitance Cf, the higher the power is required to sustain oscillation.

From Fig. 4(b) and Eq. (11), we can see that the primary source of power consumption is due to the motional resistance Rm of the resonator. Rm is proportional to g4 and inversely proportional to Q, V2ias and t2 (9). Fig. 9 shows the plots of gm versus quality factor Q, gap g, bias voltage Vbias and thickness t. In each case, all other parameters are kept fixed. To reduce gm,crit, the biasing current and static power consumption, Q, Vbias and t should be as high as possible whereas g should be as small as possible.

It is seen in Fig. 9 that for certain ranges of low quality factor, low bias voltage, high transconduction gap and process thickness, the oscillator will not be functional, no matter how large the gm is. The electrostatic gap, g, is the most crucial parameter for designing a low-power capacitive MEMS oscillator. For example, for the device under test in the work, if the gap spacing can be reduced down to only 80 nm as in [10], other parameters are kept fixed, the critical transconductance, gm,crit, as found in Fig. 5 reduced dramatically to 1.5 x 10-6(mS), theoretically. This indicates that the power consumption can be substantially reduced when the gap spacing is decreased.

3.3. ASIC circuit design

The oscillation start-up time reaches a minimum value when gm = gmopt [11]. It is also worth mentioning that to minimize the power consumption, operating the oscillator at the critical point (e.g. point A in Fig. 5) is desirable. However, to minimize the startup time and to extend the operation range, the start-up condition must be designed at the optimum point, C.

A bias and amplitude regulator circuit, Fig. 10, is designed based on previously established techniques [11,21] for crystal oscillators. At the beginning, when the oscillator has not yet started up, the

T „J X „1--1

+ V —

Q (xlO )

^bias' m

2 4 gap, g [|im]


0 20 40 thickness, t [|im]

Fig. 9. gmcrit versus quality factor Q, gap g, bias voltage Vbias and thickness t. In each case, all other parameters are kept fixed as in the extracted device parameters.

qC^Ht Jc"

Fig. 10. Bias and automatic gain control (AGC) circuit.

amplitude regulator behaves as a bias current reference circuit to provide the necessary start-up current for the Pierce core. The start-up transconductance gm,start-up is set to be higher than the critical point and close to the optimal point (Fig. 5) to accelerate oscillation build-up. As the oscillation amplitude builds up, the reference current, Iout, generated by a regulator is reduced until the vac amplitude reaches a critical point where the loop gain approaches unity. At the stable oscillation condition, the oscillator is operating at the minimum current required to address the low

1.6 1.4

>">c SO

-B-R = loo Ma b -e-R = 50 MQ b

Amplitude ofv^ [mV]

Fig. 11. Bias and automatic gain control (AGC) circuit at different value of Rb with capacitor C=5 pF. The initial bias current is set at 1.75 ^A.

power requirement. Furthermore, the ac drive voltage amplitude is also limited to reduce the impact of Duffing non-linearity in the resonator [14].

Fig. 11 shows an example of AGC current output versus amplitude input at different values of resistor Rb. The regulator requires an effective RC low-pass filter, therefore a high value of resistor Rb and capacitor C are expected. A higher regulated output range is expected at a higher corresponding value for the RC filter.

The transistor-level circuit schematic diagram for the oscillator is shown in Fig. 12. Resistor elements Rb in the Pierce core and regulator stage are implemented using sub-threshold nMOS devices (MN5, MN6, MN7) biased in the linear region to minimize layout area. Their values are set to be greater than 100 M^ by the bias circuit. MN1 is a nMOS transistor providing the gain required for the oscillation startup while the gm of MN1 is regulated by the transistor MP1. The initial drain current of MN1 is high to provide

Output stage


Pierce core




Amplitude and gm regulator

In Out

Fig. 12. Complete ASIC circuit diagram of the oscillator.

transconductance close to the gm,opt, therefore, oscillation builds up. As the amplitude at the drain of MN1, which is the driving voltage on the resonator, rises, the current provided onto MN1 through MP1 is reduced by the AGC regulator. At a certain point, the regulated current reaches the critical point, where the loop gain approaches unity, and the output voltage amplitude is saturated and remains stable.

Fig. 13 shows an example of simulation results of the circuit in Fig. 12 and the resonator model in Table 1 with topology as shown in Fig. 4. The initial gm of MN1 is set at 16 ^S. Simulations predict that at around half a second, the amplitude is saturated at about 80 mV and the total current is 330 nA at 1.2 V voltage supply. Fig. 14 plots the simulated phase noise [16] versus offset frequency for several values of temperature and bias voltage with data summarized in Table 1, Figs. 3-5,13. The feedback amplitude voltage is fixed at 80 mV to keep the resonator operates in the expected linear region. At higher temperature, the quality factor, Q, is reduced, whereas the motion resistance, Rm, is increased (Fig. 3), therefore the stability is deteriorated. When the bias voltage is creased from 10 V to 20 V, the motion resistance is reduced 4 times down to 275 kQ, the phase noise figure is improved by

0.4 0.6 Time [s]

Fig. 13. Simulation results of amplitude voltage output and total current consumption of CMOS circuit in Fig. 12 with resonator model in Table 1.

-20 -40 -60

§ -120

£ -140 -160

T=60°C, Kblas=10V, Q=22.9k,Äm=1.53M£2 T=25°C, KWas=l 0 V, Q=32k, i?m=l. 1M£2

T=25°C, Fbias=20V, Q=32k, Äm=275ki2,

10 10 10 10 10 Carrier offiet fiequency [Hz]

Fig. 14. Simulated phase noise of the oscillator under various values of temperature, T, bias voltage, Vbias, at VOut=80 mV. Qand Rm are changed with temperature as shown in Fig. 3.

10 dBc/Hz. It is predicted that higher stability of the oscillator could be achieved by increasing bias voltage and/or low temperature environmental condition.

4. Experimental results

The oscillator circuit is realized in a standard 0.35 ^m CMOS process (Fig. 15(a)) and electrically packaged together with DETF resonator on 44 pin leadless chip carrier, as shown in Fig. 15(b), via bond-wires.

Under vacuum conditions (pressure of 30 mTorr), a minimum bias voltage (Vbias=4 V) is required to maintain sustained oscillation. The oscillator can be operated on a power supply voltage (Vdd) range from 1.1 V to 3.3 V. The power dissipation of the circuit increases as Vdd is increased and Vbias is decreased.

Fig. 16 shows the measured spectrum of the oscillator output. Note that the frequency is slightly different from the open loop measurement in Fig. 2 due to process variations resulting in different centre frequencies for the two resonators employed for these experiments.

In Out

Fig. 15. (a) Micrograph of fabricated CMOS circuit. (b) Photo of the prototype package MEMS-CMOS oscillator on LCC 44 pins chip carrier.

108 110 Frequency [kHz]

Fig. 16. Measured oscillator output spectrum.

At Vbias = 10 V, Vdd = 1.2 V, the oscillator is seen to dissipate ~ 900 nA (with parasitics associated with the IO pads including ESD protection and chip carrier pad loading due to the nature of practical realization) at stable operation, which translates to a value of 400 nA of oscillator core current dissipation for no external capacitive loading at the output buffer.

A measured phase noise figure was not possible for the developed oscillator due to the unavailability of a commercial measurement system. Instead, a frequency counter (Agilent 53132A) was used to sample the oscillator output at fixed time intervals of 100 ms spacing. The Allan deviation of the measured output frequency is calculated and is shown in Fig. 17. A short-term frequency stability of less than 0.5 ppm is achieved for an averaging time t = 10 s.

As shown in Table 2 the power consumption of this work is much lower than TIA topology previously reported in [3,22] and comparable with the commercial oscillator product from SiTime [13]. The circuit reported in this work enables low-power operation for significantly higher motional resistance (1.1 MQ in this work compared with 90 kQ) and capacitive parasitics than for the work reported in [13]. The results and analysis reported in this work show that significant reduction in power consumption is possible as tighter MEMS-CMOS integration (including fully monolithic integration) becomes available.

Averaging time rfsj Fig. 17. Allan deviation plot for the Pierce oscillator.

Table 2

Capacitive MEMS oscillator comparison.

Specs This work [3] [9] [13] [22]

Frequency (Hz) 110k 77k 77k 524k 32k

Q 32k NA NA 52k 57k

Resonator size(mm) 430 x 200 505 x 435 505 x 435 NA 120 x120

Rm (Ohm) 1.1 M 4M 4M 90k 1.94 M

Topology Pierce TIA Pierce Pierce TIA

AGC Yes Yes No Yes No

Integration level 2 dies PCB 2 dies 2 dies 2 dies

Power (W) 480 n 100 ^ 21.6 ^ <288 n 2.1 ^

Best Allan sY (mHz) 5 35 650 NA NA

TIA: Transimpedance amplifier.

DETF resonator is presented. Detailed analysis and practical design considerations involved in hybrid integration of the capacitive resonator are provided to inform power optimization of the interface circuits.

The practical CMOS implementation is specifically designed for the device under test. The design is based on several factors including (i) the electrical model, (ii) measured feed-through capacitance and (iii) the nonlinear behavior of the resonator. It is designed for a maximum startup time and minimum power specification for the specified MEMS resonator. The comprehensive analysis verified by practical realization and experimental results provided in this paper provide a reference guideline for both MEMS and CMOS designers on evaluating practical considerations for the design of high-stability, power-optimized capacitive MEMS oscillators for a given process specification.

The MEMS-CMOS oscillator demonstrated a frequency stability of less than 0.5 ppm while drawing 400 nA at 1.2 V. The fabricated circuit addresses the power requirements for resonant sensor applications where power optimization is critical.

Further research will focus on design optimization to improve the linearity of the resonator so as to improve the frequency stability and noise figure. Suitable circuit-level temperature compensation techniques are also being currently explored.

5. Conclusion and future work


In this paper, the modelling, comprehensive analysis and implementation of a low-power oscillator circuit for a capacitive SOI

This work was supported by the UK Engineering and Physical Sciences Research Council (Grant no. EP/K000314/1).


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