Scholarly article on topic 'Investigation of a solder bumping technique for flip‐chip interconnection'

Investigation of a solder bumping technique for flip‐chip interconnection Academic research paper on "Materials engineering"

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Academic research paper on topic "Investigation of a solder bumping technique for flip‐chip interconnection"

Investigation of a solder bumping technique for flip-chip interconnection

David A. Hütt, Daniel G. Rhodes and Paul P. Conway

Loughborough University, Loughborough, Leicestershire, UK Samjid H. Mannan

Department of Mechanical Engineering, King's College London, London, UK David C. Whalley

Loughborough University, Loughborough, Leicestershire, UK Andrew S. Holmes

Department of Electrical and Electronic Engineering, Imperial College of Science, Technology and Medicine, London, UK

Keywords

Flip-chip, Solder bumps, Solder paste, Silicone

Abstract

As the demand for flip-chip products increases, the need for low cost high volume manufacturing processes also increases. Currently solder paste printing is the wafer bumping method of choice for device pitches down to 150-200^m. However, limitations in print quality and stencil manufacture mean that this technology is not likely to move significantly below this pitch and new methods will be required to meet the demands predicted by the technology roadmaps. This paper describes experiments conducted on carriers made from silicon for bumping of die using solder paste. An anisotropic etching process was used to generate pockets in the silicon surface into which solder paste was printed. Die were then placed against the carrier and reflowed to transfer the solder directly to the bondpads. An assessment was carried out of the potential application and limitations of this technique for device pitches at 225 and 127^m.

The authors would like to thank the EPSRC (Grant No. GR/L61767) for financial support and would also like to acknowledge the technical and financial sponsorship of DEK Printing Machines, Multicore Solders, Intarsia Corporation, Matra BAe and Mintel Semiconductor.

Received: August 1999 Revised: November 1999

Soldering & Surface Mount

Technology

12/1 [2000] 7-14

© MCB University Press [ISSN 0954-0911]

Introduction

The implementation of flip-chip assembly in many products has prompted a rapid increase in interest in this relatively old technology. As the demand for smaller, lighter and more functional products has increased, so the demand for flip-chip technology has also increased, with a concomitant requirement for high volume manufacturing solutions to reduce costs. Currently a number of flip-chip products are in mass production around the world, which utilise existing assembly processes. However, even with the implementation of flip-chip interconnect, the technology roadmaps for device packaging still point towards even higher performance products with more I/O and at a finer pitch.

For solder based flip-chip interconnection, a major step in the process route involves the deposition of solder on to the bondpads of the die for subsequent reflow on to the substrate lands. The requirements for finer pitch higher I/O components are already pushing existing low cost solder bumping technologies to their practical limits and future products may have to use higher cost, lower through-put production strategies to achieve the requisite feature sizes and pitches.

Many different methods have been employed for the solder bumping of bare die and these have been reviewed extensively in a number of publications (e.g. Rinne, 1997; Lau, 1995). Currently solder paste printing on to electroless nickel bumped die represents one of the lowest cost methods for wafer bumping for device pitches down to 150-200^m (Kloeser et al., 1998). However, limitations in print quality and solder paste volume, due to stencil manufacturing limitations and solder particle size, mean that existing printing methods are not likely to move significantly below this pitch. The attractiveness of solder paste printing as a deposition technique, due to its low cost and established infrastructure, means that methods for extending its application below 150^m pitch would be desirable.

An alternative approach to the bumping of die involves the attachment of individual pre-formed solder balls onto the bondpads. One example uses sequential placement with immediate reflow in situ by laser irradiation (Motulla et al., 1997). A number of similar processes for mass bumping use the placement of solder balls on to or into a carrier. This carrier matches the bondpad layout and holds the solder in place against the wafer during reflow (Ramos, 1998; Fujino et al., 1998; Hotchkiss et al., 1998; Lin, 1993). Many of these methods appear to have their origins in the solder ball bumping of BGA and CSP components (Ramos, 1998); however, the extension of these technologies to flip-chip geometries is non-trivial due to the reduced size of the single solder particles. This results in additional handling

complications due to the low weight of the solder balls in comparison to the forces between particles that can be generated by surface contamination and electrostatic charges. An additional complication for the use of carriers occurs when they are reflowed with the wafer. Any variation in coefficient of thermal expansion (CTE) between the carrier and the wafer can result in a significant displacement of the solder balls from the bondpads during heating from room temperature to reflow temperature. For typical reflow temperatures and with a stainless steel carrier, this can be as much as 200^m over the diameter of a 4" wafer. This has led to the suggestion of the use of a Si carrier to match the CTE of the wafer (Lin, 1993).

In order to meet the requirements for future flip-chip technology predicted by the technology roadmaps such as that by Tummala et al. (1999), methods for the bumping of die at less than 100^m pitch are necessary. This paper describes experiments to evaluate a solder bumping process that utilises a Si carrier for the reflow of solder paste on to bare die. This route combines a number of the ideas presented by other workers and is very similar to processes that have been patented by Delco Electronics Corporation (Yeh et al., 1997) and Fujitsu Limited (Ochiai et al., 1997). This paper provides an assessment of the potential application and limitations of this technique for solder bumping of devices at pitches of 225 and 127^m, together with a description of the carrier manufacturing process.

Process route

For any solder based process for the assembly of flip-chip devices, a first step in the process involves the deposition of an under-bump metallisation (UBM) on to the Al bondpad to provide a solder wettable layer. In these experiments an electroless nickel plating process was utilised to deposit a cap of NiP onto the Al surface. This process has been described elsewhere (Hutt et al., 1999) and a similar process has been implemented by a number of other groups and companies (Kloeser et al., 1998; Motulla et al., 1997; Liu, 1992; Strandjord et al., 1999).

The solder deposition process described in this paper was based on the route shown in Figure 1. First, solder paste was printed into the apertures of a "stencil", or carrier that was fabricated from Si. After this, die, which were previously electroless nickel bumped, were placed over the carrier with their bondpads aligned with the apertures. The whole assembly was then reflowed to allow the solder to melt and wet the under-bump metallisation. Finally, after cooling, the die were separated from the carrier and cleaned to remove the flux residues.

Two types of die were used in these experiments: die A consisted of a peripheral array of daisy-chain structures at

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David A. Hutt, Daniel G. Rhodes,

Paul P. Conway,

Samjid H. Mannan,

David C. Whalley and

Andrew S. Holmes

Investigation of a solder bumping

technique for

flip-chip interconnection

Soldering & Surface Mount

Technology

12/1 [2000] 7-14

225 and 300^m pitch (75^m passivation opening over the bondpad), while die B had a peripheral array of bondpads at 127^m pitch (90^m passivation opening over the bondpads). It is worth noting that for die B the combination of a pitch of only 127^m with larger pads than on die A left only 37^m between bumps. This was because die B was designed for wire bonding, while die A had been designed for flip-chip/MCM assembly. This indicates one of the difficulties of using die originally designed for wire bonding in a flip-chip product. One of the objectives, however, of the current work programme is to assess the potential adaptation of such die for flip-chip assembly. Scanning electron microscope images of the die after electroless nickel bumping are shown in Figure 2.

Si carrier manufacture

An important consideration for the implementation of this process for high volume manufacture is the availability of the Si carriers. The approach utilised for the preparation of the Si carrier substrate involved conventional micromachining technology, which is widely used in the formation of Si microstructures. The methodology is also similar to the route employed for the manufacture of conventional stencils. The starting material was a (100) oriented Si wafer, which underwent a series of process steps as are shown in Figure 3. Initially, a thermal oxide layer was grown on the surface of the Si, before a photoresist was applied. The resist was then exposed and developed to reveal the oxide layer, which was then etched away using hydrofluoric acid. Once this was complete, the photoresist was removed and the thermal oxide layer was used as the resist during the etching of the underlying silicon with an anisotropic etchant, ethylene diamine pyrocatechol (EDP). The depth of the aperture was determined by the length of time for which this etching process was carried out. After etching was complete, the thermal oxide layer was then removed in a final hydrofluoric acid treatment.

The combination of the (100) oriented Si wafer, together with the use of an aniosotropic etchant resulted in the

Figure 1

Process route for solder paste bumping of die

Carrier ___-Squeegee

Solder paste

Print solder paste into apertures in silicon carrier

Place die on to carrier and reflow

Separate die from carrier

po^o^oq _

Clean carrier for re-use

Remove flux residues

production of tapered apertures with square openings as shown in Figures 4 and 5. EDP etches the (111) plane at a rate 30-40 times slower than the (100) plane. This resulted in a taper angle of 54.7° to the surface plane, with only limited undercutting of the thermal oxide resist.

For die A, the aperture opening was 165^m with a depth of 75^m, while for die B, two different apertures were generated with openings of 95^m and 80^m at depths of 63^m and 56^m respectively. In the case of the 80^m aperture, the depth was limited by the intersection of the two sloping sides, effectively halting the etching process. This represents the physical limit of the aperture depth.

The maximum size of the aperture openings that can be generated by this process is limited only by the bondpad pitch, assuming almost no gap between cavities. However, in practice, the ability to mask and image the photoresist during the third process step ultimately determines the minimum gap between the apertures. The aperture sizes used here were smaller than the bondpad pitches on the die as these were determined by the resolution of the original photoplotted mask. This resolution could have been significantly improved by using a chromium-on-glass mask, with associated cost increases. However, this technique offers significant advantages over conventional solder paste printing stencils, where current manufacturing methods require a minimum width of web between apertures of around 50^m to maintain strength, thereby restricting the final aperture size.

Solder bumping

Initial trials of the process were conducted using die A. To fill the apertures in the Si surface with solder paste, a conventional squeegee printing process was employed. Two solder pastes were used during these studies: a water washable paste (WR) with a particle size range of 15-30^m and a rosin active (RA) paste with a particle size range from 0^m (dust) - 25^m. These pastes were printed by drawing the squeegee blade over the surface by hand. In order to obtain the best print quality, a range of squeegees were tested. This was necessary to ensure that the surface of the carrier remained free of solder particles, which would interfere with the placement of the die. While a soft rubber squeegee left very little paste over the carrier surface, it also "scavenged" a significant quantity of paste from the apertures, leading to undersized solder balls during reflow. A metal squeegee was found to offer the best finish, leaving a well filled aperture with little extra paste on the carrier surface.

After filling the carrier apertures with solder paste, individual die were placed on the carrier using a flip-chip placement system to align the bondpads with the apertures. The whole arrangement was then reflowed to allow the solder to wet the UBM and was then cooled. Following this, the die were held in contact with the Si carrier by the flux residues remaining from the solder paste. In order to release the die, the assembly was immersed in a suitable solvent for the solder paste in use and ultrasonically agitated to encourage the penetration of the solvent underneath the die. After a few seconds cleaning, the die were released from the surface of the carrier and cleaning was then continued to remove any final residues.

Cleaning of the Si carrier was similarly carried out in a solvent to remove residues from the apertures. The efficiency of this process depended greatly on the solder paste in use. It was found that, in general, water washable paste residues were the easiest to remove, leaving a clean surface after only a few seconds' ultrasonic cleaning in water, while RA paste residues required many minutes cleaning in iso-propanol.

After removal of the die from the carrier, the solder deposits were found to be distorted as though they had been "cast" in the shape of the apertures during solidification

David A. Hutt, Daniel G. Rhodes,

Paul P. Conway,

Samjid H. Mannan,

David C. Whalley and

Andrew S. Holmes

Investigation of a solder bumping

technique for

flip-chip interconnection

Soldering & Surface Mount

Technology

12/1 [2000] 7-14

(Figure 6). In order to generate well-rounded solder bumps it was necessary to carry out a further reflow of the die away from the carrier material. Figure 7 shows an area of a type A die for which this was carried out. This die was originally bumped with 6^m of electroless nickel and shows the results that are achievable with this type of device. Owing to the controlled volume of solder paste in the carrier apertures, the process generated solder balls of a very uniform height of approximately 75^m.

Attempts to extend the bumping process to die B at 127^m pitch were largely unsuccessful and only one or two pads on the die collected the solder from the apertures. Generally, it appeared that the electroless nickel bumps failed to contact the molten solder paste and the reasons for this will be discussed further in the next section.

Figure 3

Si carrier manufacturing process

Figure 2

SEM images of electroless nickel bumped die used in trials; (a) die A; (b) die B

Thermally grown oxide layer on (100) Si wafer

Oxide layer coated with photoresist

UV Light ttt

Photoresist exposed through a mask

Photoresist developed

Thermal oxide layer etched using photoresist as a mask

Photoresist removed

Silicon etched using the thermal oxide as an etch resist

Thermal oxide removed to reveal final carrier

Solder volume calculations

In order to guarantee transfer of the solder paste from the aperture on to the UBM during reflow, there must be sufficient volume of solder such that during reflow of the solder paste into a spherical ball, the resulting sphere will protrude above the carrier surface, allowing contact to be made with the electroless nickel bump. Initial estimates of the protrusion of the solder from the apertures were made during the design of the carriers. These calculations were based on the highly controlled nature of the carrier aperture etching process, which allowed the available solder volume to be predicted for apertures of different aspect ratios. Initial calculations assumed that 50 percent of the aperture volume was available as solder metal during reflow, equivalent to the solder metal content of the solder paste. With this information, the reflowed solder sphere diameter could be calculated and compared to the aperture depth to determine the extent of protrusion. However, in many situations, including the 80 and 95^m apertures, the base of the aperture was very narrow and, after reflow, the solder ball, if it remained spherical and did not wet the Si surface, would not touch the base. This situation is demonstrated in the micrograph of Figure 8a, which shows a cross-section through an 80^m wide aperture following reflow of the solder paste. Clearly the solder did not reach the bottom of the aperture and remained approximately spherical due to its surface tension. In these circumstances, for the purposes of modelling the extent of protrusion of the solder ball from

David A. Hutt, Daniel G. Rhodes,

Paul P. Conway,

Samjid H. Mannan,

David C. Whalley and

Andrew S. Holmes

Investigation of a solder bumping

technique for

flip-chip interconnection

Soldering & Surface Mount

Technology

12/1 [2000] 7-14

the aperture, it was necessary to calculate the height at which the solder ball was suspended by assuming it retained a spherical shape.

Comparison between the model figures and experimental values was made by taking measurements from carriers after reflowing the solder paste within the apertures with no die in place. After cooling the carriers, the height difference between the top of the solder ball and the carrier surface was determined using an optical microscope. The figures in Table I show the calculated and measured values of protrusion of the solder from the aperture. From these results, it can be seen that there was a significant difference between the calculated and measured values. A significant protrusion of the solder from the aperture was obtained for the die A carrier, while for die B, the top of the reflowed solder remained below the carrier surface. This largely accounts for the successful bumping of die A and the failure of this process for die B.

Figure 4

SEM images of Si carrier for die A

L- SEI EHT- 20.0 KV HD- 25 500 um 1-

SI STENCIL

Figure 5

Schematic diagram of aperture in silicon carrier

Aperture Opening

I Undercutting (8)

Aperture Depth (D)

(100) Plane

Figure 6

Solder bumped die A after removal from carrier

L- SEI EHT- 20.0 KU WD- 25 m 200 um I-

SI STENCIL

In the calculations described above, it was initially assumed that 50 percent of the aperture volume would be filled with solder metal, equivalent to the solder metal content in the solder paste. However, as the volume of the aperture decreases and the particle size of the solder paste remains the same, this assumption becomes incorrect due to inefficient packing of the particles in the pocket and empty space in corners. This was thought to be the reason for the differences between the expected solder volumes and measured values. In order to estimate the packing efficiency of the solder particles in the cavities, computer simulations were performed based on a method similar to that proposed by He and Ekere (1998). This method involved generating a number of spheres with a size distribution within the limits of the solder paste. These spheres were then randomly placed into the model aperture, allowing them to overlap with each other and the aperture walls. Following this, the simulation was started and the spheres were allowed to move away from each other, to remove the overlaps. If a solution to the model could be found with no overlaps, then the number of particles was increased and the simulation re-run. This was continued until a maximum volume of solder was found. Comparison of the total volume of the solder spheres with the aperture volume produced a figure for the packing efficiency, expressed as a percentage. By using a random filling routine to begin the simulation, rather than simply optimising the packing by placing smaller particles in corners or in the gaps between larger particles, the packing efficiency values obtained should be similar to the real printing process. Hence, the data presented here do not

David A. Hutt, Daniel G. Rhodes,

Paul P. Conway,

Samjid H. Mannan,

David C. Whalley and

Andrew S. Holmes

Investigation of a solder bumping

technique for

flip-chip interconnection

Soldering & Surface Mount

Technology

12/1 [2000] 7-14

indicate the maximum possible packing efficiency, but the most probable packing efficiency expected for solder paste printing.

For the model calculations performed in this study, detailed information regarding the solder paste particle size distribution was not available, so a normal distribution was assumed. Example calculations for the apertures used in this study are shown in Table II, together with comparative data obtained from the experiments. For the larger 165^m apertures, the calculations indicated that the paste particle size had little effect on the packing efficiency and the assumption of 50 percent of the aperture volume reflowing as solder metal was still correct. However, for the smaller apertures, the packing efficiency was found to decrease to as little as 32 percent. From Table II it can be seen that there is now better agreement between calculation and

Figure 7

Bumped die A after second reflow to centre solder deposits

I- SE1 EHT- 20.0 KW UD- 26 500 MI" I-

'ample 17

PHOTO- 22

L V f ♦ f # 1

experiment for the various aperture sizes, particularly the smaller ones. As expected, the model predicts a higher packing density for the finer particle size paste (0-25^m), which the experimental results appear to reflect. However, following the reflow process with the 0-25^m paste, a number of small solder particles were observed in the aperture that were unattached to the bulk solder ball, indicating incomplete reflow of the paste. This resulted in the reflowed solder ball being smaller in volume than predicted and led to reduced protrusion of the ball from the aperture. This highlights one of the major difficulties in using solder pastes with finer particle sizes; as the ratio of solder surface area to volume rises, the flux activity can be insufficient to allow all the particles to coalesce. Even with an RA flux in the paste the solder did not reflow completely.

The reason for the remaining differences between experimental observation and calculation are unclear, but may reflect the fact that the solder volume calculations assume a normal particle diameter distribution and the real printing process may not achieve such a high packing density. Using a distribution skewed towards smaller particles in the computer simulations leads to more efficient packing, and similarly an excess of larger particles leads to lower volume fractions.

Deformation of the solder spheres due to their weight and interaction with the flux/Si interfaces may also account for the differences between theory and experiment. In particular, for the smaller apertures, the solder is expected to be suspended in the aperture and may be slightly deformed into the base of the pocket. It is difficult to ascertain from the micrograph in Figure 8a whether the ball is deformed, due to the problems associated with polishing a soft material like solder, which can smear. However, the solder ball in the large aperture of Figure 8b is clearly not spherical, as it appears to be wider than it is tall. This may explain some of the larger differences for the bigger apertures.

It is apparent from the results in Table II that for die A, a good degree of protrusion of the molten solder was observed and this led to a good yield for the die used in these experiments. The above calculations assume that the UBM cannot project into the aperture; however, one advantage of the use of electroless nickel as the UBM for die A was that the height of the bump allowed it to protrude into the aperture, ensuring a good contact between the bump and the solder paste (Figure 9a). This interaction could be enhanced by using die with thicker (e.g. 30^m) electroless nickel bumps (Figure 9b). Unfortunately for die B, bumps significantly thicker than 6^m could not be used. This was due to the isotropic nature of the electroless nickel process, which produced both outward as well as upward growth of the deposits and therefore could not be applied to die B as this would have shorted the bumps together. Furthermore, the width of the electroless nickel bump on die B was larger than the aperture opening and therefore the bumps could not protrude into the apertures to contact the solder paste (Figure 9c). This was exacerbated by any solder paste particles left on the carrier surface following printing (Figure 9d). The lack of good contact between the bumps and the solder paste during reflow resulted in almost complete failure for this bumping process when applied to die B.

In these studies no gold flash was applied over the nickel surface following bumping and the unpreserved nickel surface produced a number of failures due to the solder paste not wetting the nickel pads. In subsequent experiments, the solderability of the die was improved by applying a solder finish to the bumps using a simple dipping procedure (Hutt et al., 1999). This involved the fluxing of the die followed by immersion in a solder bath. This method left a small cap of solder on top of the nickel bump, which had a thickness of around 13^m for die A. In addition to creating a more wettable surface, this procedure also increased the height of the bump, which subsequently increased its protrusion into the aperture of the Si carrier

David A. Hutt, Daniel G. Rhodes,

Paul P. Conway,

Samjid H. Mannan,

David C. Whalley and

Andrew S. Holmes

Investigation of a solder bumping

technique for

flip-chip interconnection

Soldering & Surface Mount

Technology

12/1 [2000] 7-14

after placement (Figure 9e). The resulting enhanced contact between bump and paste and more solderable surface also improved the yield of the bumping process.

From the solder volume calculations presented above, the height of the final solder bump could be estimated, based on the diameter of the electroless nickel bump, using a straightforward calculation for a spherical cap (Nguty and Ekere, 1999). For a 6^m thick NiP bump on die A, the predicted bump height was 83^m (including the electroless nickel thickness), in fair agreement with the measured bump height of 75^m. It should be remembered that the spherical cap equation assumes wetting of a flat surface, while the electroless nickel bumps have a rounded edge,

Figure 8

Cross-section of reflowed solder paste in Si carrier apertures; (a) aperture opening of 80^m (die B); (b) aperture opening of 165^m (die A)

which would require more detailed calculations to model accurately. However, of more importance, the solder volume estimates indicate that even if the process could be applied to die B, the small size of the apertures and the large surface area of the bumped bondpads would lead to extremely small solder bumps of less than 20^m in height. These bumps would be too small to form reliable flip-chip joints and this indicates that there is a limit to the usefulness of this technique for use with fine pitch devices with large bondpads.

An indication of the approaching limit of this technique can be seen with the 30^m electroless nickel bumps on die A. As the electroless nickel process used for the UBM was isotropic, the diameter of the bondpads on the die with 30^m high NiP bumps was significantly larger than the original passivation opening of 75^m (i.e. final diameter of 135^m). Figure 10 shows a solder bump on one such die. Here the volume of solder was insufficient to wet the sides of the large nickel bumps and a bump shape was formed that was determined by the surface tension of the solder and the low contact angle made with the rounded edge of the electroless nickel bump.

Discussion

The process described above features a number of aspects that could allow a low cost reliable process to be achieved. In particular, the use of solder paste provides a relatively low cost source of solder and the technology and infrastructure to print solder paste and place and align wafers is already available in most stencil printing machines. This route also has potentially limited environmental impact, comparable to conventional stencil printing, but with significant advantages over alternative processes that require imaging and development of photoresists (Salonen and Salmi, 1994) or the disposal of used carrier materials such as polyimide tapes (Hotchkiss et al., 1998).

An important feature of the present process is that it does not rely on the paste releasing from the stencil apertures, as in the conventional printing process. This not only increases the available solder volume, but also allows a simplified paste formulation to be used with a greater choice of flux vehicles. This is particularly useful for the important process step of releasing the die from the carrier, which involves dissolving the flux residues and cleaning of the carrier apertures. Presently, this step of the process would make application of this method to whole wafers problematic due to the difficulties associated with encouraging solvents to penetrate between the wafer and carrier. If this process could be carried out efficiently by good design of the solder paste for easy cleaning, then a significant increase in throughput could be achieved, together with safer handling of bumped wafers.

The Si carriers used in this work were made from a relatively low-cost source material that allowed the carrier to expand and contract at the same rate as the wafer during reflow, maintaining the registration between the apertures and the bondpads. In addition, the Si provided a non-solder wettable surface to allow easy release of the bumped die. The manufacturing process for the carriers used existing technologies that could be easily applied to a high volume process. This is particularly important, since in a high through-put wafer bumping line, a number of carriers would be required to allow some to be printed and die placed, while others were reflowed and cleaned. It is not envisaged, though, that preparing multiple carriers of the same design would significantly increase the tooling costs.

The major limitation of this technique becomes apparent from the solder volume calculations above. The quantity of solder that can be deposited is limited severely by the aperture shape, although by using solder pastes with different particle size distributions, the efficiency of the printing process could be improved. In the case of die B,

V:: SOLDER .N APERTURE

there is insufficient solder metal volume in the aperture to form a ball that protrudes far enough above the carrier surface to contact the chip. However, even if contact could be made, the volume that would be deposited would not be sufficient to form a suitable flip-chip joint, due to the large area of the bondpads. Further investigations are planned to look at alternative carrier manufacturing processes to generate apertures with greater volumes by using different orientation silicon wafers and etching methods.

In order to increase the volume of solder, it was also found possible to apply the process twice on the same die. This effectively doubled the solder bump volume. Figure 11

Table I

Predicted and measured protrusion of reflowed solder paste above carrier surface, assuming 50 percent of aperture volume is available as solder metal (susp. indicates that solder ball is expected to be suspended in tapered aperture)

Calculated Predicted Measured

solder sphere protrusion of protrusion of

Aperture Aperture Aperture diameter after sphere above solder above

Die type opening/^m depth/^m volume/^m3 reflow/^m carrier/^m carrier/^m

A 165 75 10.1 x105 99 24 8 ± 2

B 95 63 2.02 x 105 58 12* -4±3

B 80 56 1.21 x 105 49 10* -4 ±4

Notes: * Solder ball is expected to be suspended in tapered aperture

Table II

Calculated and measured protrusion of reflowed solder paste above carrier surface (susp. indicates that solder ball is expected to be suspended in tapered aperture)

Calculated

maximum Calculated Predicted Measured

packing solder sphere protrusion of protrusion of

Aperture Aperture Solder paste efficiency diameter after sphere above solder above

opening/^m depth/^m particle size/^m (percent) reflow/^m carrier/^m carrier/^m

165 75 15-30 (WR) 47 97 22 8 ± 2

165 75 0-25 (RA) 50 99 24 10 ±2

95 63 15-30 (WR) 34 51 2* -4 ± 3

95 63 0-25 (RA) 38 53 5* -2 ±2

80 56 15-30 (WR) 32 42 1* -4 ±4

80 56 0-25 (RA) 36 44 3* -4 ±2

Notes: * Solder ball is expected to be suspended in tapered aperture

Figure 9

Schematic diagrams of chip placement and solder reflow: (a) conventional process with 6^m electroless nickel bumps on die A; (b) process with 30^m electroless nickel bumps on die A; (c) 6^m electroless nickel bumps on die B;

(d) paste residue on carrier during reflow of die B;

(e) solder dipped die A placed on carrier

(c) (d)

Solder Dip Cap

David A. Hutt, Daniel G. Rhodes,

Paul P. Conway,

Samjid H. Mannan,

David C. Whalley and

Andrew S. Holmes

Investigation of a solder bumping

technique for

flip-chip interconnection

Soldering & Surface Mount

Technology

12/1 [2000] 7-14

Figure 10

Solder bumped die A with 30^m thick electroless nickel bump

Figure 11

Die A with 30^m electroless nickel bumps following double solder application process

shows solder bumps on top of 3^m electroless nickel (compare with Figure 10) and shows clearly how the increase in solder volume has allowed the solder to cover the sides of the electroless nickel bumps. This is possible, as the volume printed into the apertures is constant and is simply added to the volume already on the die. By contrast, if a repeat printing stage were to be carried out with a conventional stencil printing process, the volume of solder would not be doubled, as the solder bump already formed on the die would occupy a significant part of the stencil aperture, limiting the amount of additional paste that could then be printed. An alternative process route therefore suggests itself for some applications: owing to the faster conventional stencil printing process this could be used to apply the first solder volume to the die while a subsequent Si carrier based process could be used to increase the final bump height. This could be useful for boosting the solder volume in applications where one printing process would not be sufficient.

David A. Hutt, Daniel G. Rhodes,

Paul P. Conway,

Samjid H. Mannan,

David C. Whalley and

Andrew S. Holmes

Investigation of a solder bumping

technique for

flip-chip interconnection

Soldering & Surface Mount

Technology

12/1 [2000] 7-14

Conclusion

This paper has evaluated the potential application of a low cost solder bumping route for fine pitch flip-chip assembly. This technology offers a reliable method to use solder paste as a bumping medium for devices around 200^m pitch, comparable to conventional printing. However, for very fine pitch devices, difficulties due to solder volume restrictions mean that this method may have limitations. Careful design of the carrier aperture size and shape and solder paste particle size distribution needs to be carried out to ensure the maximum bumping yield.

References

Fujino, J., Takaki, S., Hayashi, K., Izuta, G. and Hirota, J. (1998), "Development of ball bump forming technology using solder paste and new simplified CSP'', Proceedings IEEE / ECTC Conference, pp. 442-7.

He, D. and Ekere, N.N. (1998), "Computer simulation of powder compaction of spherical particles'', Journal of Materials Science Letters, Vol. 17 No. 20, pp. 1723-5.

Hotchkiss, G., Amador, G., Jacobs, L., Stierman, R., Dunford, S., Hundt, P., Beikmohamadi, A., Cairncross, A., Gantzhorn, J., Quinn, B. and Saltzberg, M. (1998), "Tacky dots transfer of solder spheres for flip-chip and electronic package applications'', Proceedings IEEE/ECTC Conference, pp. 448-53.

Hutt, D.A., Mannan, S.H., Whalley, D.C. and Conway, P.P. (1999), "A maskless, low cost multi-chip-module assembly process'', Proceedings InterPack, EEP, Vol. 26 No. 2, pp. 1705-11.

Kloeser, J., Heinricht, K., Kutzner, K., Jung, E., Ostmann, A. and Reichl, H. (1998), "Fine pitch stencil printing of Sn/Pb and lead free solders for flip-chip technology'', IEEE Trans. CPMT, part C, Vol. 21, pp. 41-9.

Lau, J.H. (1995), Flip-Chip Technologies, McGraw-Hill, New York, NY.

Lin, P.T. (1993), "Method of transferring solder balls on to a semiconductor device", US Patent No. US5219117.

Liu, J. (1992), "Development of a cost-effective and flexible bumping method for flip-chip interconnections", Hybrid Circuits, September, pp. 25-31.

Motulla, G., Kasulke, P., Heinricht, K., Ostmann, A., Zakel, E., Reichl, H., Aszdasht, G. and Kloeser, J. (1997), "A low cost bumping process for flip-chip technology using electroless Ni/ Au bumping and solder ball placement", Advances in Electronic Packaging Conference EEP, Vol. 19 No. 1, pp. 57-64.

Nguty, T.A. and Ekere, N.N. (1999), "Modelling of flip-chip

assembly stand-off height", Proceedings InterPack, EEP, Vol. 26 No. 1, pp. 55-63.

Ochiai, M., Ueda, H., Sono, M., Yamaguchi, I., Mitobe, K., Otake, K., Kasai, J., Kamebara, N., Yamagishi, Y., Mizukoshi, M., Yamada, Y. and Abe, S. (1997), "Process for forming solder balls on a plate having apertures using solder paste and transferring the solder balls to semiconductor device", US Patent No. 5643831.

Ramos, R. (1998), "Flux-free placement and attach of solder spheres", Advanced Packaging, May, pp. 36-9.

Rinne, G.A. (1997), "Solder bumping methods for flip-chip packaging", Proceedings IEEE/ ECTC, pp. 240-7.

Salonen, J. and Salmi, J. (1994), "A flip-chip process based on electroplated solder bumps", Physica Scripta, Vol. T54, pp. 230-3.

Strandjord, A.J.G., Popelar, S.F. and Erickson, C.A. (1999),

"Commercialization of a low cost wafer bumping process for flip-chip applications", Proceedings IMAPS Flip-chip Advanced Technology Workshop, Chateau Elan, Braselton, Georgia.

Tummala, R., White, G. and Sundaram, V. (1999), "SOP:

microelectronics systems packaging for twenty-first century: prospects and progress", Proceedings IMAPS Europe, Harrogate, UK, pp. 327-35.

Yeh, S., Higdon, W.D. and Cornell, R.E. (1997), "Solder bump transfer device for flip-chip integrated circuit devices", US Patent No. 5607099.