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Investigation of Cell Structure and Doping for Low-On-Resistance SiC Metal-Oxide-Semiconductor Field-Effect Transistors with Blocking Voltage of 3300 V

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http://dx.doi.org/10.7567/JJAP.52.04CP03

Investigation of Cell Structure and Doping for Low-On-Resistance SiC Metal-Oxide-Semiconductor Field-Effect Transistors with Blocking Voltage of 3300 V

Kenji Hamada1, Naruhisa Miura1;2, Shiro Hino1;2, Tsuyoshi Kawakami1, Masayuki Imaizumi1, Hiroaki Sumitani3, and Tatsuo Oomori2;3

1 Advanced Technology R&D Center, Mitsubishi Electric Corporation, Amagasaki, Hyogo 661-8661, Japan

2 R&D Partnership for Future Power Electronics Technology (FUPET), Minato, Tokyo 105-0001, Japan 3Power Device Works, Mitsubishi Electric Corporation, Fukuoka 819-0192, Japan

Received September 21, 2012; revised December 3, 2012; accepted December 7, 2012; published online March 21, 2013

We have investigated the effect of n-type doping into the junction field-effect transistor region (JFET doping) on the static characteristics of 3300-V-class 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The JFET doping technique is significantly effective in reducing the on-resistance of SiC MOSFETs without degradation of the blocking characteristics when the MOS cells are properly designed. The JFET doping reduces the temperature coefficient of the resistance in the JFET region, leading to lower on-resistance of the SiC MOSFETs at high temperatures. © 2013 The Japan Society of Applied Physics

1. Introduction

Power electronics has so far made a significant contribution to saving energy and natural resources with its highly efficient power conversion technologies, where power devices play the central roles. Silicon (Si) has been used as a conventional material for power devices. However, the power devices fabricated using Si are approaching their performance limits. Recently, silicon carbide (SiC) has attracted much attention since it exhibits exceptional material properties compared with conventional Si, such as a wider band gap, a higher critical electric field strength, and a higher thermal conductivity. SiC power devices are expected as next-generation alternatives to Si power devices and demonstrate overwhelming characteristics in terms of loss reduction.

SiC has a potential to be applicable with a wide range of voltage ratings compared with Si owing to its remarkable characteristic. Recently, prototype devices of over 10 kV rating have been reported, which is absolutely unrealizable with Si. These particularly include SiC bipolar devices such as insulated gate bipolar transistors or pin diodes.1-8) In the case of these bipolar devices, conductivity modulation between electrons and holes makes a significant contribution to reducing their on-resistances. On the other hand, SiC unipolar devices, especially metal-oxide-semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention owing to their high speed switching operation and low on-resistance compared with Si bipolar devices. Discrete SiC MOSFETs have been developed by many institutes for middle-voltage classes from 600 to 2000V.9-13) Efficiency improvement and miniaturization of power inverters and converters by embedding SiC MOS-FETs have also been reported.14-18-1 Furthermore, unipolar device technology has a potential to realize power devices with higher blocking voltages such as 3300 V, which are required for railway systems. Development of diodes with 3300 V rating and their application to construct a hybrid SiC module have already been reported;19-211 however, extensive experimental studies on MOSFETs are still very limited for realizing a full SiC module.22 231 Therefore, in this study, we thoroughly investigated the 3300-V-class SiC MOSFETs from the viewpoint of the cell structure dependence on static

electrical characteristics. From the experimental and simulation results, the effectiveness of doping into the junction field-effect transistor region (JFET doping, JD) of a MOSFET is demonstrated on realizing low on-resistance even at high temperatures.

2. Fabrication of MOSFETs

The SiC doubly implanted vertical MOSFETs were fabricated on n-type 4H-SiC wafers with a 30 pm lightly doped n-type drift layer. The net donor concentration (ND - NA) is equal to 3.0 x 1015 cm-3. ND - NA and the thickness of the layer are designed by numerical simulation to block 3300 V with a low leakage current. The device employs an originally developed field limiting ring structure for the termination, which guarantees a stable avalanche breakdown at approximately 4 kV. The doping condition for JD was carefully selected in advance by process and device simulations since it significantly influences both the on-resistance and breakdown voltage. The depth and doping concentration of the JD region were designed to be about 1 pm and 1 x 1017 cm-3, respectively, which were realized by multiple high-energy nitrogen implantations. Note that the profile of the nitrogen was designed not to influence any channel characteristics nor the electric field of the gate oxide; therefore, shallow nitrogen implantation was not performed. The MOSFET consists of a parallel conjunction of square-shaped unit cells with channel lengths (Lch) of 0.4-1.6 pm, JFET lengths (LJ) of 1.6-3.6 pm, and a cell pitch (Lfp) of 11 pm. The devices were fabricated with active areas of 4.8 x 10-5 and 2.0 x 10-3 cm2. Activation of implanted dopants was carried out at about 1700 °C. A 50-nm-thick gate oxide layer was formed by thermal oxidation with subsequent nitridation. The electrodes were formed by Ni silicidation for the source and drain. The cross-sectional MOSFET structure is shown in Fig. 1.

Results and Discussion

MOS cell structure dependence of static characteristics

Static electrical characterization was performed MOSFETs at room temperature. Figure 2 shows

for the

dependence of the specific on-resistance (Ron,sp) of MOSFETs fabricated with and without JD. Ron,sp was estimated at

Fig. 1. Cross section of 3300-V-class SiC MOSFET (unit cell).

<N a 20

LCh = 0.7 |im 1 1

O • •

w/o JD w/ jD

1.0 1.5 2.0 2.5 3.0 3.5 4.0

Lj [|im]

Fig. 3. JFET length dependence of specific on-resistance of MOSFETs fabricated with and without JD at room temperature (active area: 2.0 x 1Q-3 cm2).

LJ for the devices without JD. Since Ron,sp of the devices with JD is smaller than that without in the entire LJ range studied here, the effect of the depletion layer in the JFET region as well as the spread resistance influence Ron,sp.

Figures 4(a) and 4(b) show an analysis of the resistive components of Ron,sp of the devices with and without JD, respectively. The resistances of the channel (Rch) and the JFET with drift (Rj + Rdrift) were estimated by test element group (TEG) analyses. Rch was calculated using the MOSFET whose parasitic resistance was negligibly smaller than Rch. RJ + Rdrif was calculated using the MOSFET having an electrically shunted channel. Rch decreases as LJ decreases regardless of the application of JD. This is due to the increase in channel width density while Lch of 0.7 pm and Lfp of 11 pm are fixed. On the other hand, RJ + Rdrif

0.5 1.0 1.5 Lch [|m]

Fig. 2. Channel length dependence of specific on-resistance of MOSFETs fabricated with and without JD at room temperature (active area: 4.8 x 10-5 cm2).

a drain current (Ids) of 100 A/cm2 and a gate voltage (Vgs) of 15 V. Ron,sp decreases monotonically as Lch decreases and shows a similar trend regardless of the application of JD. The smaller Ron,sp for the devices with JD is due to the reduction in JFET resistance. The channel mobility was deduced to be about 22cm2/(V-s) in both structures. Figure 3 shows the LJ dependence of Ron,sp. Ron,sp increases drastically for a short LJ, and this increase occurs at a longer

30 25 20 15 10 5 0

2.6 3.0 3.2 3.6 Lj [|m]

25-----R

w/o JD

20 15 10 5 0

Rdrift

2.6 3.0 3.2 3.6 Lj [|m]

Fig. 4. Analysis of the resistive components of specific on-resistance with JD (a) and without JD (b) at room temperature.

increases significantly as LJ decreases, and the effect is more pronounced for the devices without JD. This result suggests that lowering RJ + Rdrift is quite effective in reducing MOSFET total resistance.

Figure 5 shows the LJ dependence of avalanche breakdown voltage (BVDS) at VGS of —10 V. BVDS decreases as LJ increases for the devices with JD, indicating that for a longer LJ, the electric field at the edge of the p-well becomes higher. In order to verify numerically, we calculated the electric field at the edge of the p-well region (ESiC) at a drain voltage (VDS) bias of 3300 V. The ESiC values are

1.0 1.5 2.0 2.5 3.0 3.5 4.0

Lj [|im]

Fig. 5. JFET length dependence of avalanche breakdown voltage of MOSFETs fabricated with and without JD at room temperature (active area: 2.0 x 1Q-3 cm2).

400 300

^GS = 20 V

KGS = 15 V

^GS- s = 0 10V 5 V

p20 10

Qi < 10

4 • 1

• < lot

o< >o< >0 T

• w/o JD Ow/ JD

50 100 150 200 250 Temperature [°C]

• w/o JD Ow/ JD Rdrift) T O

i • o > ^

(b) • < r >

>oc >o< >o<

50 100 150 200 250 Temperature [°C]

234 KdS [V]

Fig. 7. Temperature dependence of (a) on-resistance and (b) variation of JFET, drift and channel resistances compared with the values at 25 °C. The data were taken for the devices with and without JD.

Fig. 6. Typical Ids-Vds characteristics of MOSFETs with JD at room temperature. The device has the JFET length of 2.2 pm (active area: 4.8 x 10-5 cm2).

2.1 MV/cm at LJ of 1.6 pm and 2.3MV/cm at LJ of 3.0 pm for the devices without JD. In contrast, the ESiC values are 2.6 MV/cm at LJ of 1.6 pm and 3.1 MV/cm at LJ of 3.0 pm for the devices with JD. A longer LJ and adoption of JD cause a higher electric field near the breakdown. Therefore, it is important to appropriately design LJ and doping to ensure a high avalanche breakdown voltage with low on-resistance. Figure 6 shows the 1DS-VDS characteristics of the MOSFETs with JD having LJ of 2.2 pm. A low Ron,sp of 14 m^ cm2 and a high BVDS of 3843 V, which is about 94% of the theoretical value, are realized.

3.2 Temperature dependence of on-resistance

The temperature dependence of the static behavior of the MOSFETs is investigated. Figure 7(a) shows the temperature dependence of Ron,sp of the MOSFETs with LJ of 3.0 pm and Lch of 0.7 pm. Ron,sp increases from 12 m^ cm2 at room temperature to 20 m^ cm2 at 150 °C for the devices with JD, while it increases from 23 to 42 m^ cm2 for the devices without JD. It could be seen that the MOSFET with JD exhibits both a lower Ron,sp and a smaller temperature coefficient compared with that without JD. On the other hand, there was no obvious difference in threshold voltage (Vh) between the two devices. The Vh at VDS = 10 V was

about 2 V at room temperature and it decreased to about 1 V at 150 °C. The results were analyzed using TEG devices and summarized in Fig. 7(b), where the temperature dependences of RJ + Rdrift and Rch are plotted. The Rch values and the temperature coefficients of Rch for the two devices are almost the same, since JD was designed not to affect the channel characteristics. Their negative coefficients should be due to the increase in channel effective mobility at high temperatures. On the other hand, RJ + Rdrift increases at higher temperatures, and the temperature coefficient is small for the device with JD. While intervalley scattering mainly affects electron mobility with a negative temperature coefficient above 300K,24) the effect of ionized impurity scattering on electron mobility is enhanced as the doping concentration increases. Since electron mobility under ionized impurity scattering has a positive temperature coefficient, the temperature dependence of electron mobility in the JFET region with JD becomes small. This is confirmed by the experimental data from the Hall-effect measure-ments,25) where the temperature-dependent electron mobility in n-type 4H-SiC epilayers with different nitrogen-doping densities is obtained. These results suggest that the JFET doping is quite effective in realizing 3300-V-class SiC MOSFETs with low on-resistance at high temperatures.

4. Summary

We investigated the effect of JFET doping on the static characteristics of 3300-V-class 4H-SiC MOSFETs. The JFET doping technique is significantly effective in reducing

the on-resistance of SiC MOSFETs. The low on-resistance of 14 mfi cm2 with a high avalanche breakdown voltage of 3843 V is realized for the device with properly designed MOS cells. The JFET doping reduces the temperature coefficient of resistance in the JFET region, leading to a decreased on-resistance of the SiC MOSFETs at high temperatures.

Acknowledgements

A part of this study was conducted under a joint research contract with the New Energy and Industrial Technology Development Organization (NEDO) of Japan as a "Novel Semiconductor Power Electronics Project Realizing Low Carbon-Emission Society''.

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