Selection of DC voltage magnitude using Fibonacci series for new hybrid asymmetrical multilevel inverter with minimum PIV Academic research paper on "Electrical engineering, electronic engineering, information engineering"

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Alexandria Engineering Journal (2014) xxx, xxx-xxx

FACULTY OF ENGINEERING ALEXANDRIA UNIVERSITY

Alexandria University Alexandria Engineering Journal

www.elsevier.com/locate/aej www.sciencedirect.com

ORIGINAL ARTICLE

Selection of DC voltage magnitude using Fibonacci series for new hybrid asymmetrical multilevel inverter with minimum PIV

M.R. Banaei *, A. Fazel Bakhshayesh

Electrical Engineering Department, Faculty of Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran Received 29 November 2013; revised 11 June 2014; accepted 14 June 2014

KEYWORDS

Multilevel inverter; Asymmetrical; Fibonacci series; PIV

Abstract Multilevel inverters are suggested to obtain high quality output voltage. In this paper, a new hybrid configuration is proposed, obtained by cascading one four switches H-bridge cell with a family of multilevel inverters. In addition, by the use of specific sequence for value of DC sources named Fibonacci series, asymmetrical topology of proposed inverter is introduced. Main advantages are that proposed inverter has least Peak Inverse Voltage (PIV) than other conventional multilevel converters in both symmetric and asymmetric modes. Also, this topology doubles the number of output levels using only one cascaded four switches H-bridge cell. The PCI-1716 DAQ using PC has been used to generate switching pulses in experimental results. For presenting valid performance of proposed configuration, simulation results carried out by MATLAB/SIMULINK software and the validity of the proposed multilevel inverter is verified by experimental results.

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1. Introduction

High-power industrial applications of converters have been revolutionized in the recent decades by the advent of multilevel converters [1]. Lately, multilevel converters have presented an important development to reach higher power with increasing

* Corresponding author. Tel.: +98 914 4017344; fax: +98 4124327566. E-mail addresses: m.banaei@azaruniv.edu (M.R. Banaei), fazel@spta. ir (A. Fazel Bakhshayesh).

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voltage levels [2]. Also many multilevel inverter configurations and pulse width modulation (PWM) techniques are presented to improve the output voltage harmonic spectrum [3-5]. Multilevel inverters can be considered as voltage synthesizers, wherein the output voltage is synthesized from many discrete smaller voltage levels. Compared with the traditional two-level voltage inverter, the main advantages of the multilevel inverters are having smaller output voltage step, lower harmonic components, better electromagnetic compatibility and lower switching losses [2,6-9]. They can also operate at both fundamental switching frequency and higher switching frequencies in accord with the implementations [9]. But, the main drawbacks of the multilevel inverters are the use of a larger number of semiconductors and a complex control circuitry and needing the balancing of the voltage at the boundaries of capacitors [10,11].

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From among voltage source multilevel converters, cascaded and modular multilevel converters offer several benefits such as possibility of eliminating ac side filters and interfacing transformer in some applications where it is appropriate, low dv/dt and switching losses as converter switches operate at low frequency [12,13].

In the present paper, a new hybrid symmetric and hybrid asymmetric topology of multilevel inverter has been investigated. In symmetrical mode the value of PIV and the number of switches versus other conventional symmetric converters has been reduced. For magnitude selection of DC voltage sources in asymmetrical mode Fibonacci series [14], has been used. This cause significant reduction in total switches PIV with respect to other multilevel topologies. Simulation results and comparison studies and experimental results verify validity of theoretical consideration.

2. Case study

2.1. Conventional cascaded H-bridge multilevel inverter

One of the basic structures for multilevel inverters is cascaded H-bridge inverter. Fig. 1 shows a single phase cascaded multilevel inverter.

In cascaded H-bridge multilevel inverters each DC source is connected to different stages. If all DC voltage sources in Fig. 1, equal to Vdc = 1pu, the converter is known as symmetric multilevel inverter. In symmetric topology, each cell can generate three voltage levels + Vdc, 0, — Vdc. The number of output voltage levels can be obtained by:

m = 2n + 1

and PIV is given by:

PIV = 4nVdc

where n is the number of DC sources and m is the number of voltage levels. To obtain large number of output voltage levels, asymmetric multilevel inverter can be used. In binary topology

dû Ôh

of asymmetric cascaded multilevel inverter, maximum output voltage levels and PIV are given by:

m = 2n+1 - 1 if Vdcl = 2-1Vdc for i = 1,2,..., n (3) PIV = 4(2n - 1)Vdc (4)

and in trinary topology, maximum output voltage levels and PIV are given by:

m = 3n if Vda = 3i-1Vdc for i = 1,2,..., n PIV = 2(3n - 1) Vdc

2.2. A symmetrical topology of multilevel inverter

In [15], a new symmetrical topology of multilevel inverter is introduced, as presented in Fig. 2. In this configuration all of negative and positive levels can be obtained.

This configuration consists of DC voltage sources and (2n + 2) unidirectional switches. Maximum output voltage can be obtained as follows:

VOmax = V + V2 + ... + Vn.

V = V2 = ... = Vn

For Vn = Vdc, maximum output voltage will be Vomax = nVdc. The number of output voltage levels and PIV can be obtained by:

m = 2n + 1 PIV = 4nVdc

(8) (9)

(1) Vdc

(2) ÇP'

Figure 3 Four switches three level H-bridge inverter.

Figure 1 Single phase cascaded multilevel inverter.

Figure 2 Family of multilevel inverters proposed in [15].

--100 "У - ^100 v 6 У--

г-р-

-—100 v У -^100 v

S1 , I S3 /\ I S,

•ц g и

Frequency (

Figure 5 Operation of 15-level proposed symmetric converter: (a) The configuration of a 15-level proposed symmetric MLI; (b) Carriers and reference signals; (c) Output voltage; (d) Frequency spectrum of output voltage.

3. Proposed topology

3.1. Hybrid symmetric converter

In this paper, to increase the output voltage levels only four switches H-bridge inverter in Fig. 3 has been mixed by specific topology shown in Fig. 2 as series (Fig. 4).

In proposed converter, with n DC sources, in order to double the number of output voltage levels in specific configuration basic structure, H-bridge DC source value is selected half of the minimum value of basic structure DC voltage sources.

For example, if all DC voltage sources in Fig. 4 are equal to Vdc = 1pu, selected value for H-bridge DC source will be 1 Vdc — 0.5pu.

In Fig. 4 value of VH—bridge is —iimiHl — —.. Since in hybrid symmetric topology, DC voltage sources in basic structure are the same, this inverter can be known as a symmetric multilevel inverter. The number of output voltage levels, is obtained by m = 4n — 1, where n is the number of DC voltage sources.

The PIV value of hybrid symmetric topology is given by:

PIV = (4w - 2) Vdc

Table 1 ON state switches lookup table for symmetric

proposed topology.

Output ON state switches

voltage

+ 350 (S1 S4 S6 , S8, Sh2; Sh4)

+ 300 (S1 S4 S6 Sg Sh2; Sh3) 0r (S1; S S 5; S8; Sh1; Sh4)

+ 250 (S1 S4 S6 Sg Sh1 Sh3) or (S2, S4 S6 Sg Sh2; Sh4)

(S1 S4 S6 S7 Sh2 Sh4

+ 200 (S2 S4 S6 Sg Sh2 Sh3) or (S2, S4 S6 Sg Sh1 Sh4)

(S1 S4 S6 S7 Sh2 Sh3) or (S1, S4 S6 S7 Sh1 Sh4)

+ 150 (S2 S4 S6 Sg Sh1 Sh3) or (S1, S4 S6 S7 Sh1 Sh3)

(S1 S3 S6 Sg Sh2 Sh4 or (S2, S4 S6 S7 Sh2 Sh4)

(S1 S4 S5 Sg Sh2 Sh4

+ 100 (S1 S3 S6 Sg Sh2 Sh3) or (S1, S3 S6 Sg Sh1 Sh4)

(S2 S4 S6 S7 Sh2 Sh3) or (S2, S4 S6 S7 Sh1 Sh4)

(S1 S4 S5 Sg Sh2 Sh3) or (S1, S4 S5 Sg Sh1 Sh4)

+ 50 (S1 S3 S6 Sg Sh1 Sh3) or (S2, S4 S6 S7 Sh1 Sh3)

(S1 S4 S5 Sg Sh1 Sh3) or (S2, S4 S5 Sg Sh2 Sh4)

(S1 S3 S6 S7 Sh2 Sh4 or (S2, S3 S6 Sg Sh2 Sh4)

(S1 S4 S5 S7 Sh2 Sh4

0 (S2 S4 S5 Sg Sh2 Sh3) or (S2, S4 S5 Sg Sh1 Sh4)

(S2 S3 S6 Sg Sh2 Sh3) or (S2, S3 S6 Sg Sh1 Sh4)

(S1 S4 S5 S7 Sh2 Sh3) or (S1, S4 S5 S7 Sh1 Sh4)

-50 (S2 S4 S5 S7 Sh2 Sh4) or (S1, S3 S5 Sg Sh2 Sh4)

(S2 S3 S6 S7 Sh2 Sh4) or (S2, S4 S5 Sg Sh1 Sh3)

(S1 S3 S6 S7 Sh1 Sh3) or (S2, S3 S6 Sg Sh1 Sh3)

(S1 S4 S5 S7 Sh1 Sh3)

-100 (S2 S4 S5 S7 Sh2 Sh3) or (S2, S4 S5 S7 Sh1 Sh4)

(S1 S3 S5 Sg Sh2 Sh3) or (S1, S3 S5 Sg Sh1 Sh4)

(S2 S3 S6 S7 Sh2 Sh3) or (S2, S3 S6 S7 Sh1 Sh4)

-150 (S1 S3 S5 S7 Sh2 Sh4) or (S2, S3 S5 Sg Sh2 Sh4)

(S2 S4 S5 S7 Sh1 Sh3) or (S1, S3 S5 Sg Sh1 Sh3)

(S2 S3 S6 S7 Sh1 Sh3)

-200 (S1 S3 S5 S7 Sh2 Sh3) or (S1, S3 S5 S7 Sh1 Sh4)

(S2 S3 S5 Sg Sh2 Sh3) or (S2, S3 S5 Sg Sh1 Sh4)

-250 (S2 S3 S5 S7 Sh2 Sh4) or (S1, S3 S5 S7 Sh1 Sh3)

(S2 S3 S5 Sg Sh1 Sh3)

-300 (S2 S3 S5 S7 Sh2 Sh3) or (S2, S3 S5 S7 Sh1; Sh4)

-350 (S2 S3 S5 S7 Sh1 Sh3)

Table 2 ON state switches lookup table for asymmetric proposed topology.

Output voltage

ON state switches

450 (S1 S4 S6 Sg Sh2 Sh4)

400 (S1 S4 S6 Sg Sh1 Sh3) or (S1 S4 S6 Sg Sh1 Sh4)

350 (S1 S4 S6 Sg Sh2 Sh3) or (S2 S4 S6 Sg Sh1 Sh4)

300 (S2 S4 S6 Sg Sh2 Sh3) or (S2 S4 S6 Sg Sh1 Sh4)

250 (S2 S4 S6 Sg Sh1 Sh3) or (S1 S3 S6 Sg Sh2 Sh4)

(S1 S4 S6 S7 Sh2 Sh4)

200 (S1 S3 S6 Sg Sh2 Sh3) or (S1 S3 S6 Sg Sh1 Sh4)

(S1 S4 S6 S7 Sh2 Sh3) or (S1 S4 S6 S7 Sh1 Sh4)

150 (S1 S3 S6 Sg Sh1 Sh3) or (S1 S4 S6 S7 Sh1 Sh3)

(S2 S3 S6 Sg Sh1 Sh4) or (S2 S4 S6 S7 Sh2 Sh4)

(S1 S4 S5 Sg Sh2 Sh4)

100 (S2 S3 S6 Sg Sh2 Sh3) or (S2 S3 S6 Sg Sh1 Sh4)

(S2 S4 S6 S7 Sh2 Sh3) or (S2 S4 S6 S7 Sh1 Sh4)

(S1 S4 S5 Sg Sh2 Sh3) or (S1 S4 S5 Sg Sh1 Sh4)

50 (S2 S3 S6 Sg Sh1 Sh3) or (S2 S4 S6 S7 Sh1 Sh3)

(S1 S4 S5 Sg Sh1 Sh3) or (S2 S4 S5 Sg Sh2 Sh4)

(S1 S3 S6 S7 Sh2 Sh4)

(S2 S4 S5 Sg Sh2 Sh3) or (S2 S4 S5 Sg Sh1 Sh4)

(S1 S3 S6 S7 Sh2 Sh3) or (S1 S3 S6 S7 Sh1 Sh4)

50 (S1 S4 S5 S7 Sh2 Sh4) or (S1 S3 S5 Sg Sh2 Sh4)

(S2 S3 S6 S7 Sh2 Sh4) or (S2 S4 S5 Sg Sh1 Sh3)

(S1 S3 S6 S7 Sh1 Sh3)

100 (S1 S4 S5 S7 Sh2 Sh3) or (S1 S4 S5 S7 Sh1 Sh4)

(S1 S3 S5 Sg Sh2 Sh3) or (S1 S3 S5 Sg Sh1 Sh4)

(S2 S3 S6 S7 Sh2 Sh3) or (S2 S3 S6 S7 Sh1 Sh4)

150 (S2 S4 S5 S7 Sh2 Sh4) or (S2 S3 S5 Sg Sh2 Sh4)

(S1 S4 S5 S7 Sh1 Sh3) or (S1 S3 S5 Sg Sh1 Sh3)

(S2 S3 S6 S7 Sh1 Sh3)

200 (S2 S4 S5 S7 Sh2 Sh3) or (S2 S4 S5 S7 Sh1 Sh4)

(S2 S3 S5 Sg Sh2 Sh3) or (S2 S3 S5 Sg Sh1 Sh4)

250 (S1 S3 S5 S7 Sh2 Sh4) or (S2 S4 S5 S7 Sh1 Sh3)

(S2 S3 S5 Sg Sh1 Sh3)

300 (S1 S3 S5 S7 Sh2 Sh3) or (S1 S3 S5 S7 Sh1 Sh4)

350 (S2 S3 S5 S7 Sh2 Sh4) or (S1 S3 S5 S7 Sh1 Sh3)

400 (S2 S3 S5 S7 Sh2 Sh3) or (S2 S3 S5 S7 Sh1 Sh4)

450 (S2 S3 S5 S7 Sh1 Sh3)

The operation of the proposed multilevel converter is described by Fig. 5. Fig. 5(a) shows the configuration of a 15-level proposed multilevel inverter. The carrier and reference signals are shown in Fig. 5(b). The number of carrier signals is obtained by «carrier = m — 1 = 14 [15]. Fig. 5(c) shows the output voltage of Vo. The output voltage frequency spectrum is given in Fig. 5(d). The magnitude of each voltage source in basic structure is considered , V1 = V2 = V3 = 100 V and the value of voltage source in H-bridge cell is FH-br!dge = 50 V. Table 1 shows ON state switches lookup table for each output voltage level.

3.2. Hybrid asymmetric converter

One disadvantage of topology shown in Fig. 2 is that DC voltage source magnitude cannot be determined as binary and tri-nary asymmetric states.

In this paper a new method to determine DC voltage magnitudes is proposed based on special sequence which is taken from Fibonacci series [14]; as follows:

for V = 1pu, V2 = 1pu

then Vi = V_i + Vi_2, i = 3,4, 5,...

Hence , without increase in the number of components , voltage levels increase and waveform being high quality and so structure has been asymmetric. Thus, DC voltage sources value , can be obtained as follows:

jr Ui _(1 _ U)i jr ■ -, o ,

Vi =-p5-Vdc, I = 1,2, 3,..., n

where n is the number of DC voltage sources and u is called Golden Ratio that is equal to:

1 + \/5 2

In asymmetrical proposed topology the number of voltage levels is equal to:

4x/5((1 _ u)"+' _ U+1) m —-----1

Time (s) (b)

0.015 Time (s)

0.025 0.03

Frequency (Hz) (d)

Figure 6 Operation of 19-level proposed asymmetric converter: (a) The configuration of a 19-level proposed asymmetric MLI; (b) Carriers and reference signals; (c) Output voltage; (d) Frequency spectrum of output voltage.

And PIV is obtained by:

PIV = 2 + 2

,un-1 -(1 - u)n

+ U+i-ffiU)^, I Vdc (15)

Thus, value of DC voltage sources in basic structure will be {—dc, —dc, 2—dc, 3—dc, 5—dc, 8—dc, 13—dc,...}. Fig. 6(a) shows, 19 level hybrid asymmetric proposed topology with n = 4 DC voltage sources.

The value of each voltage source in basic structure is considered, {100 V, 100 V, 200 V} and the value of voltage source in H-bridge cell is —H-bridge = 50 V. The carrier and reference signals are shown in Fig. 6(b). The number of carrier signals is nCarrier = m — 1 = 18. Output voltage of —o is presented in Fig. 6(c). Fig. 6(d) shows the output voltage frequency spectrum of the proposed asymmetric topology. Table 2 shows ON state switches lookup table for each output voltage level for asymmetric proposed topology.

Table 3 Number of switches and PIV value for conventional symmetric inverters and proposed.

Symmetric inverter CMI Semi cascade Proposed

m (number of levels) 2n + 1 2n + 1 4n - 1

PIV 4nVdc (6n - - 2) Vdc (4n - - 2) Vdc

Switches (IGBT) 4n 2n + - 2 2n + 4

Figure 7 Comparison number of switches and PIV of symmetric topologies: (a) Number of switches; (b) PIV (pu).

Table 4 Number of switches and PIV value for conventional asymmetric inverters and proposed. Asymmetric inverter Binary CMI Trinary CMI Binary semi cascade Proposed m (number of levels) 2n+1 - 1 3n 2n+1 -1

PIV (2n+2 - 4)Vdc (2 x 3n - 2)Vdc (6 x 2n - 6)Vdc

Switches (IGBT) 4n 4n 2n + 4

4%/5((1-v)n+1-yn+') 5

PIV = (2 + 2 u 2n + 4

(1-v)n

■ + 2Y. v

-(1-vf P5

-(1-vf

4. Comparison between the proposed multilevel inverter and other topologies

4.1. Symmetric topology

In this section, the proposed topology is compared with other three multilevel inverters. The first comparison index is PIV. The main purpose of this paper, was obtaining least PIV with respect to other topologies of multilevel inverters. In symmetrical hybrid proposed topology, PIV of switches is given by PIV = (4n — 2) Vdc. Table 3, summarizes the number of switches and PIVs for the symmetric cascaded multilevel inverter and symmetric topology of [6] and also proposed symmetric topology respectively, where n is the number of DC voltage sources. As shown in Fig. 7(a), for generate same output levels number, the number of switches for symmetric proposed topology is fewer than other topologies. Also, Fig. 7(b) presents that with the same number of output voltage levels, switches PIV for symmetric proposed topology is fewer.

4.2. Asymmetric topology

Table 4, summarizes the number of switches and PIV for the binary and trinary cascaded multilevel inverter and asymmetric topology of [6] and proposed topology respectively.

Fig. 8 compares number of switches and switches PIV, versus the number of voltage levels, for proposed topology and other asymmetric topologies. As shown in Fig. 8, although the number of switches for synthesizing same number of voltage levels, is further with respect to trinary and binary cascaded multilevel inverter (Fig. 8(a)), but this defect is negligible versus need for least PIV. Switches PIV of proposed asymmetric multilevel inverter, has least value with respect to other topologies. This minimizes total cost of inverter. Comparison PIV is shown in Fig. 8(b).

5. Experimental results

In order to validate proposed topology, an experimental prototype of the 19-level asymmetric proposed inverter is implemented. The PCI-1716 DAQ has been used to generate switching pulses. The 74HC573 current buffer has been used to preservation DAQ from high current. The inverter consists of 12 switches power M0SFET-IRFP460 and TLP250 as MOSFET driver. Fig. 9 shows the experimental circuit setup. The parameters of resistive inductive load are 40X and 1H. Carrier waveforms for switching algorithm assumed constant by values of {0.5, 1.5, 2.5, 3.5,...,17.5}. It should be noted that the values of DC voltage sources are {25 V, 50 V, 50 V, 100 V} according to Fibonacci series.

— binary CMI --trinary CMI

■■■ binary proposed in [2]

— ■ asymmetric proposed

1000 800 600 400 200

— binary CMI --trinary CMI ■■■ binary proposed in [2] — ■ asymmetric proposed

« * ■ _______

0 50 100 150 200 250 300

Number of Voltage Levels

Figure 8 Comparison number of switches and PIV of asymmetric topologies: (a) Number of switches; (b) PIV (pu).

Figure 9 Hardware implementation of 19-level proposed asymmetric multilevel inverter.

Fig. 10(a) depicts experimental waveforms of the voltage and current of load. Fig. 10(b and c) show the output voltage of basic structure (VB) and H-bridge cell (VH), respectively. As shown in Fig. 10(a-c), since the four switches H-bridge inverter has been mixed by basic structure as series, the output

Figure 10 Experimental results: (a) The output voltage (10 x 10V/ Div) and resistance voltage (10 * load current) (10 x 0.5 V/Div) (b) Output voltage of basic structure, VB(10 x 10 V/Div); (c) Output voltage of H-bridge cell, VH(10 x 2V/Div); (d) Frequency Spectrum.

voltage levels VO doubled with respect to basic structure voltage. Also the output voltage THD and output current THD are measured respectively 6.79% and 3.34%.

6. Conclusions

In this paper a new topology of symmetric and asymmetric multilevel inverters has been presented. In asymmetric configuration for determination of DC voltage source magnitude, Fibonacci series has been used. This method results in a remarkable reduction in both the PIV and cost of the converter. This is because the selected MOSFETs (or IGBTs) can be of low cost due to low applied voltage with respect to other configurations. Validity of the analysis has been proved by simulation and experimental results.

References

[1] V. Dargahi, A.K. Sadigh, M. Abarzadeh, M.R.A. Pahlavani, A. Shoulaei, Flying capacitors reduction in an improved double flying capacitor multicell converter controlled by a modified modulation method, IEEE Trans. Power Electron. 27 (9) (2012) 3875-3887.

[2] M.R. Banaei, F. Mohajel, M.R. Kazemi, Jannati Oskuee, A new mixture of hybrid stacked multicell with half-cascaded converter to increase voltage levels, IET Power Electron. 6 (7) (2013) 1406-1414.

[3] A. Nabae, Takahashi, H. Agaki, A new neutral point-clamped PWM inverter, IEEE Trans. Ind. Appl. IA-17 (5) (1981) 518-523.

[4] J. Rodrigues, S. Bernet, B. Wu, J.O. Pontt, S. Kouro, Multilevel voltage-source-converter topologies for industrial medium-voltage drives, IEEE Trans. Ind. Electron. 54 (6) (2007) 2930-2945.

[5] M.R. Banaei, H. khounjahan, E. Salary, Single source cascaded transformers multilevel inverter with reduced number of switches, IET Power Electron. 5 (9) (2012) 1748-1753.

[6] M.R. Banaei, E. Salary, Verification of new family for cascade multilevel inverters with reduction of components, J. Elect. Eng. Technol. 6 (2) (2011) 245-254.

[7] M. Sadeghi, S.H. Hosseini, R. Alizadeh, M.R. Banaei, New mixed stacked multicell converter with interesting advantages, IET Power Electron. 5 (8) (2012) 1298-1304.

[8] Mohamad Reza Banaei, Pouya Asadi Shayan, H. khounjahan, A solution for selective harmonic optimization in diode clamped inverters using radial basis functions neural networks, IET Power Electron. 7 (5) (2014) 1106-1112.

[9] J. Rodriguez, J.S. Lai, F.Z. Peng, Multilevel inverters: a survey of topologies, controls, and applications, IEEE Trans. Ind. Electron. 49 (4) (2002) 724-738.

[10] K.A. Corzine, Y.L. Familiant, A new cascaded multi-level H-bridge drive, IEEE Trans. Power Electron. 17 (2002) 125-131.

[11] J.S. Lai, F.Z. Peng, Multilevel converters—a new breed of power converters, IEEE Trans. Ind. Appl. 32 (1996) 509-517.

[12] G.P. Adam, B. Alajmi, K.H. Ahmed, S.J. Finney, B.W. Williams, New flying capacitor multilevel converter, in: Industrial Electronics (ISIE), 2011 IEEE International Symposium on.

[13] S.J. Huang, J.C. Wu, Design and operation of cascaded active power filters for the reduction of harmonic distortions in a power system, Gener. Transm. Distrib. IEE Proc. 146 (1999) 193-199.

[14] Yang Hai, Fu Ruiqin, An equation involving the Fibonacci numbers and Smarandache primitive function, in: Multimedia Technology (ICMT), 2011 International Conference on.

[15] M.R. Banaei, E. salary, Analysis of a generalized symmetrical multilevel inverter, J. Circ. Syst. Comput. 20 (2) (2011) 299-311.